Showing papers on "Voltage-controlled oscillator published in 2000"

On the use of MOS varactors in RF VCOs

Abstract: This paper presents two 1.8 GHz CMOS voltage-controlled oscillators (VCOs), tuned by an inversion-mode MOS varactor and an accumulation-mode MOS varactor, respectively. Both VCOs show a lower power consumption and a lower phase noise than a reference VCO tuned by a more commonly used diode varactor. The best overall performance is displayed by the accumulation-mode MOS varactor VCO. The VCOs were implemented in a standard 0.6 /spl mu/m CMOS process.

A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver

Abstract: A fully integrated 5-GHz phase-locked loop (PLL) based frequency synthesizer is designed in a 0.24 /spl mu/m CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. On-chip spiral inductors with patterned ground shields are also optimized to reduce the VCO and ILFD power consumption and to maximize the locking range of the ILFD. The synthesizer consumes 25 mW of power of which only 3.8 mW is consumed by the VCO and the ILFD combined. The PLL has a bandwidth of 280 kHz and a phase noise of -101 dBc/Hz at 1 MHz offset frequency. The spurious sidebands at the center of adjacent channels are less than -54 dBc.

A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications

Abstract: One approach to implementation of low-phase-noise integrated fixed-frequency local oscillators (LOs) for use as the RF LO in a blockdown-convert receiver architecture for PCS wireless communications down-converts the entire RF band to a lower frequency using a fixed-frequency LO. This allows new approaches to the implementation of low-phase-noise oscillators with low-Q components. The technique uses a DLL-based frequency multiplier to synthesize a RF LO whose phase noise is closely related to that of the reference crystal and not dependent on the phase noise of a VCO. An experimental prototype generates a 900 MHz signal and is designed to meet the requirements of the IS-137 standard. The device achieves a phase noise of -123dBc/Hz at a 60 kHz offset frequency with 39 mA overall current consumption from a 3.3 V supply. This prototype was fabricated in 0.35 /spl mu/m double-poly five-metal CMOS.

Charge pump with perfect current matching characteristics in phase-locked loops

Abstract: Conventional CMOS charge pump circuits have some current mismatching characteristics. The current mismatch of the charge pump in the PLLs generates a phase offset, which increases spurs in the PLL output signals. In particular, it reduces the locking range in wide range PLLs with a dual loop scheme. A new charge pump circuit with perfect current matching characteristics is proposed. By using an error amplifier and reference current sources, one can achieve a charge pump with good current matching characteristics. It shows nearly perfect current matching characteristics over the whole VCO input range, and the amount of the reference spur is <-75 dBc in the PLL output signal. The charge pump circuit is implemented in a 0.25 /spl mu/m CMOS process.

Radio frequency control for communications systems

Abstract: The present invention provides for a system and method for improvement of radio transmitter and receiver frequency accuracy for a local radio communication unit that communicates digital data with a remote communication unit. In the local unit the received radio signal is down-converted, and converted to complex baseband digital samples by an analog-to-digital converter. A downlink digital phase rotator applies a fine frequency shift to the samples in accordance with a receiver frequency offset command. The resultant baseband signal is used by the data demodulator and by a receiver frequency error estimator to obtain receiver frequency errors. A data modulator generates baseband complex samples which are shifted in carrier frequency by an integrated uplink digital phase rotator in accordance with a transmitter frequency offset command. The modulated samples are then converted by a digital-to-analog converter and upconverted in frequency for radio transmission to the remote unit. The local oscillator signals for both upconverter and downconverter are phase locked to a reference frequency generated by a VCXO. An automatic frequency control (AFC) function nulls the transmitter and receiver frequency error by the frequency adjustment commands to the uplink and downlink phase rotators or to the VCXO digital-to-analog converter (VCXO DAC) by feedback control principals based on measured receiver frequency error. During frequency track mode when communications between local and remote units are possible, the AFC only adjusts radio frequency via phase rotator commands and the VCXO command remains fixed, thereby avoiding communications performance degradation by VCXO frequency quantization error due to the VCXO DAC. The AFC adjusts VCXO frequency only during a preliminary acquisition mode prior to data communications, or to back out excessively large frequency offsets accumulated in the downlink and uplink phase rotators during track mode. When a VCXO adjustment is made in track mode, phase rotator adjustments are simultaneously applied to cancel the errors in transmitter and receiver radio frequencies caused by the step change due to VCXO frequency quantization thereby mitigating VCXO frequency quantization noise.

Discharge lamp lighting device

Abstract: PROBLEM TO BE SOLVED: To allow a circuit for lighting a fluorescent lamp to inhibit source voltage fluctuation and fluctuation of light rays caused by fluctuation of ambient temperature. SOLUTION: A power detecting part 5 detects via a resistance R1 a voltage signal proportional to a current in a fluorescent lamp and detects via voltage dividing resistances R3, R4 a voltage signal proportional to the voltage of the fluorescent lamp, and the instantaneous values of the two voltage signals at every moment are multiplied via a multiplying circuit U41, with this multiplication output smoothed via a low-pass filter U42 to detect the average power value S5 of the fluorescent lamp. Next, a control circuit 4 compares the average power value S5 with a reference voltage value Vref via an error amplifier U2, and controls the drive circuit U3 of an inverter circuit 3 via a voltage controlled oscillator U1 so that the difference therebetween becomes zero, thereby varying the switching frequencies of switching elements T1, T2.

A CMOS self-calibrating frequency synthesizer

Abstract: A programmable phase-locked-loop (PLL)-based frequency synthesizer, capable of automatically adjusting the nominal center frequency of the voltage-controlled oscillator (VCO) to an optimum value is described. In fully integrated PLLs, the VCO output frequency should be tunable over a wide range of frequencies, covering the desired range of the synthesizer output frequencies, for all processing variations and operating conditions. A wide tuning range realized by making the VCO gain K/sub o/ large has the unwanted effect of increasing the phase noise at the output of the VCO, and hence the PLL as well. In this work, the wide tuning range is realized by digital control, with process variability managed through self-calibration. The PLL is only required to pull the oscillator output frequency to account for the digital quantization, temperature variations, and some margin. This allows the K/sub o/ to be small, with better noise performance resulting. The prototype self-calibrating frequency synthesizer, capable of operating from 80 MHz to 1 GHz, demonstrates a measured absolute jitter of 20-ps rms at 480-MHz operating frequency. The prototype IC is fabricated in a 0.35-/spl mu/m 3-V digital CMOS process.

Microwave MEMS-based voltage-controlled oscillators

Abstract: A microwave voltage-controlled oscillator (VCO) based on coupled bonding wire inductors and microelectromechanical system (MEMS)-based variable capacitors for frequency tuning is demonstrated in this paper. The MEMS-based variable capacitors were fabricated in a standard polysilicon surface micromachining technology. The variable capacitors have a nominal capacitance of 1.4 pF and have a Q factor of 23 at 1 GHz and 14 at 2 GHz. The capacitance is variable from 1.4 to 1.9 pF as the tuning voltage is swept from 0 to 5 V. The VCO, fabricated in a 0.5 /spl mu/m CMOS technology, was assembled in a ceramic package where MEMS and CMOS dice were bonded together. The oscillator operates at 2.4 GHz, achieves a phase noise of -122 dBc/Hz at 1 MHz offset from the carrier, and exhibits a tuning range of 3.4%.

IQ modulation systems and methods that use separate phase and amplitude signal paths and perform modulation within a phase locked loop

Abstract: A digital signal processor generates in-phase, quadrature-phase and amplitude signals from a baseband signal. A modulator modulates the in-phase and quadrature-phase signals to produce a modulated signal. A phase locked loop is responsive to the modulated signal. The phase locked loop includes a controlled oscillator having a controlled oscillator input. An amplifier includes a signal input, amplitude control input and an output. The signal input is responsive to the controlled oscillator output and the amplitude control input is responsive to the amplitude signal. The phase locked loop that is responsive to the modulated signal includes a controlled oscillator output and a feedback loop between the controlled oscillator input and the controlled oscillator output. The feedback loop includes a mixer that is responsive to a local oscillator. The modulator may be placed in the phase locked loop. In particular, the modulator may be placed in the feedback loop between the controlled oscillator output and the mixer, between the local oscillator and the mixer, or between the mixer and the controlled oscillator input.

A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noise upconversion minimization

Abstract: A fully integrated 2-GHz very low-phase-noise LC-tank voltage-controlled oscillator (VCO) set with flicker noise upconversion minimization is presented. Using only integrated planar inductors, the measured phase noise is as low as -125.1 dBc/Hz at 600-kHz offset and -138 dBc/Hz at 3 MHz. The excellent phase-noise performance is achieved by means of an in-house-developed integrated inductor simulator optimizer. To minimize the upconversion of flicker noise to 1/f/sup 3/ phase noise, a flicker-noise upconversion factor is defined, which can easily be extracted from circuit simulation. The technique is applied to demonstrate the relationship between the flicker-noise upconversion and the overdrive level of the oscillators' MOS cross-coupled pair and to develop circuit balancing techniques to even further reduce the flicker-noise upconversion. The 1/f/sup 3/ phase-noise corner is minimized to be less than 15 kHz. The VCO's are implemented in a three-metal layer, 0.65-/spl mu/m BiCMOS process, using only MOS active devices.

Digital fractional phase detector

Abstract: A digital fractional phase detector is provided to realize a frequency synthesizer architecture that naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information. The digital fractional phase detector is capable of accommodating a quantization scheme to measure fractional delay differences between the significant edge of the VCO output clock and a reference clock by using a time-to-digital converter to express the time difference as a digital word for use by the frequency synthesizer.

The effect of varactor nonlinearity on the phase noise of completely integrated VCOs

Abstract: This work discusses variations in phase noise over the tuning range of a completely integrated 1.9-GHz differential voltage-controlled oscillator (VCO) fabricated in a 0.5-/spl mu/m bipolar process with 25-GHz f/sub t/. The design had a phase noise of -103 dBc/Hz at 100 kHz offset at the top of the tuning range, but the noise performance degraded to -96 dBc/Hz at 100 kHz at the bottom of the tuning range. It was determined that nonlinearities of the on-chip varactors, which led to excessively high VCO gain at the bottom of the tuning range, were primarily responsible for this degradation in performance. The VCO has a power output of -5 dBm per side. Calculations predict phase noise with only a small error and provide design insight for minimizing this effect. The oscillator core drew 6.4 mA and the output buffer circuitry drew 6 mA, both from a 3.3-V supply.

A 4.5-mW 900-MHz CMOS receiver for wireless paging

Abstract: An ultralow-power 900-MHz receiver implemented on a single CMOS chip is intended for use in FLEX wireless paging. The receiver uses an indirect conversion to zero intermediate frequency (IF) to suppress the flicker noise corner in the second mixer to less than 1 kHz. Various techniques for low-power design, most of them unique to CMOS, are presented, with theoretical support and experimental verifications. The receiver, fabricated in a 0.25-/spl mu/m standard CMOS process, achieves 7.4-dS noise figure at 1.6 kHz with -25-dBm IIP3 on a 1.5 V supply. The voltage-controlled oscillator (VCO) has a phase noise of -98 dBc/Hz at 25 kHz offset. The nominal receiver bias current of 3 mA is higher than the expected 2 mA because of unanticipated losses in coupling capacitors.

An architecture of high-performance frequency and phase synthesis

Abstract: Frequency synthesis has many applications in today's commercial electronic and telecommunication system design. Some techniques exist which can be used to generate a frequency that is an integer or fractional multiple of a reference frequency. This architecture is used to generate a signal of any desired frequency in a certain range from multiple reference signals with same frequency but different phases. These reference signals may come from a voltage-controlled oscillator (VCO) which is close looped with a reference clock by a phase-lock loop (PLL). This architecture provides some unique features, superior quality, and ease of implementation. In some cases, the synthesized frequency is time-average frequency. The signal can be treated as a carrier signal frequency modulated by another signal. Various phase-shifted versions and duty cycle versions of this signal can also be generated from this architecture. This architecture also has direct application to spread spectrum clock generation.

A 1.3 GHz low-phase noise fully tunable CMOS LC VCO

Abstract: This paper presents a low-phase noise CMOS LC-VCO, in which a complete compensation of the component spread, due to process variations, can be done. The LC tank is made of a metal-oxide-silicon varactor and a bondwire and a spiral inductor in series. The trade-off between VCO gain variations and phase noise is introduced. The measurements performed on a prototype, powered by a 2-V supply, realized in a digital CMOS process, are presented. The oscillation frequency can be varied in the range 1.1-1.45 G-Hz. The measured phase noise at an offset of 600 kHz from a 1.3-GHz carrier is -119 dBc/Hz, with 6-mA current consumption.

Short pulse microwave transceiver

Abstract: Harmonic techniques are employed to leverage low-cost, ordinary surface mount technology (SMT) to high microwave frequencies where tight beamforming with a small antenna makes reliable, high-accuracy pulse-echo radar systems possible. The implementation comprises a 24 GHz short-pulse transceiver comprised of a pulsed harmonic oscillator employed as a transmitter and an integrating, pulsed harmonic sampler employed as a receiver. The transmit oscillator generates a very short (0.5 ns) phase-coherent harmonic-rich oscillation at a sub-multiple of the actual transmitter frequency. A receiver local oscillator operates at a sub-multiple of the transmit frequency and is triggered with controlled timing to provide a very short (0.5 ns), phase-coherent local oscillator burst. The local oscillator burst is coupled to an integrating harmonic sampler to produce an integrated, equivalent-time replica of the received RF. The harmonic techniques overcome four major problems with non-harmonic approaches: 1) expensive, precision assembly, 2) high local oscillator noise, 3) sluggish oscillator startup, and 4) spurious local oscillator injection locking on external RF. The transceiver can be used for automotive backup and collision warning, precision radar rangefinding for fluid level sensing and robotics, precision radiolocation, wideband communications, and time-resolved holographic imaging.

A low-phase-noise CMOS LC oscillator with a ring structure

Abstract: This LC ring oscillator is an architectural experiment to reduce the phase noise of an LC oscillator even further with a ring type structure. An LC oscillator with a special ring type structure performs phase noise filtering and attenuation. To prove the concept, several LC-ring oscillators are fabricated in 0.6 /spl mu/m, single-poly, triple-metal, CMOS. The three-stage LC-ring oscillator has -132 dBc/Hz measured phase noise at 600 kHz offset frequency from a 900 MHz carrier.

5-GHz SiGe HBT monolithic radio transceiver with tunable filtering

Abstract: A wide-band CDMA-compliant fully integrated 5-GHz radio transceiver was realized in SiGe heterojunction-bipolar-transistor technology with on-chip tunable voltage controlled oscillator (VCO) tracking filters. It allows for wide-band modulation schemes with bandwidth up to 20 MHz. The receiver has a single-ended single-sideband noise figure of 5.9 dB, more than 40 dB on-chip image rejection, an input compression point of -22 dBm, and larger than 70 dB local-oscillator-RF isolation. The phase noise of the on-chip VCO is -100 and -128 dBc/Hz at 100 kHz and 5 MHz offset from the carrier, respectively. The transmitter output compression point is +10 dBm. An image rejection better than 40 dB throughout the VCO tracking range has been demonstrated in the transmitter with all spurious signals 40 dB below the carrier. The differential transceiver draws 125 mA in transmit mode and 45 mA in receive mode from a 3.5-V supply.

Delta-sigma based dual-port modulation scheme and calibration techniques for similar modulation schemes

Abstract: PLL frequency synthesizers and their calibration techniques are described. The PLL frequency synthesizers are used to generate digital modulation of a carrier signal. A digital frequency divider in the feedback path of the loop has its division ratio controlled by a digital Δ-Σ modulator. The modulation of the carrier is achieved by applying a modulation signal to the input of the Δ-Σ modulator and to the input of the voltage-controlled oscillator of the PLL. The high frequency path and low frequency path of the modulation signal must be adjusted with respect to one another in order to obtain a good modulation. As the low frequency path can be accurately set, the calibration is performed only on the high frequency path. Digital calibration techniques for the high frequency path are described.

A 1.9-GHz CMOS VCO with micromachined electromechanically tunable capacitors

Abstract: This paper presents a 1.9-GHz CMOS voltage-controlled oscillator (VCO) where the resonant circuit consists of micromachined electromechnically tunable capacitors and a bonding wire inductor. The tunable capacitors were implemented in a MUMP's polysilicon surface micromachining process. These devices have a nominal capacitance of 2.1 pF and a quality factor (Q-factor) of 9.3 at 1.9 GHz. The capacitance is variable from 2.1 pF to 2.9 pF within a 4-V control, voltage range. The active circuits were fabricated in a 0.5-/spl mu/m CMOS process. The VCO was assembled in a ceramic package where the MUMP's and CMOS dice were bonded together. The experimental VCO achieves a phase noise of -98 dBc/Hz and -126 dBc/Hz at 100 kHz and 600 kHz offsets from the carrier, respectively. The tuning range of the VCO is 9%. The VCO circuit and the output buffer consume 15 mW and 30 mW from a 2.7-V power supply, respectively.

Time division multiplex data recovery system using close loop phase and delay locked loop

Abstract: A time division multiplex data recovery system using a closed-loop phase lock loop (PLL) and delay locked loop (DLL) is disclosed. In other words, one closed loop comprises both a phase locked loop (PLL) and a delay locked loop (DLL) in a novel time division multiplex data recovery system. This new architecture comprises a 4 stage Voltage Controlled Oscillator (VCO) used to generate 8 clock signals, 45 degrees phase shifted from one another, for 8 receivers to do the oversampling. An interpolator tracks the received data signal and feeds it back to the Phase/Frequency Detector (PFD). The PFD has a second input of the reference clock which the PFD uses along with the interpolator input to correct the frequency of the PLL. The PLL operates at a high bandwidth. The DLL's bandwidth is several orders lower than the PLL. The DLL activates only a multiplexer and an interpolator continuously, thereby drawing a minimum amount of power.

SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application

Abstract: An integrated 10 Gb/s clock and data recovery (CDR) circuit is fabricated using SiGe technology, It consists of a linear-type phase-locked loop (PLL) based on a single-edge version of the Hogge phase detector, a LC-tank voltage-controlled oscillator (VCO) and a tri-state charge pump. A PLL equivalent model and design method to meet SONET jitter requirements are presented. The CDR was tested at 9.529 GB/s in full operation and up to 13.25 Gb/s in data recovery mode. Sensitivity is 14 mV/sub pp/ at a bit error rate (BER)=10/sup -9/. The measured recovered clock jitter is less than 1 ps RMS. The IC dissipates 1.5 W with a -5 V power supply.

A wide tuning range gated varactor

Abstract: A wide tuning range gated varactor for radio frequency (RF) applications is described in this paper. The gated varactor is a three-terminal device. The third terminal helps achieve an improved tuning range. The measured tuning range of the varactor exceeds /spl plusmn/50%. The new device can be implemented with a standard CMOS process without any post-processing. A 2 GHz prototype voltage-controlled oscillator (VCO) is implemented using the new varactor in a 0.35-/spl mu/m CMOS process. The VCO achieved a sensitivity of 220 MHz/V.

A frequency and symbol synchronization system for OFDM signals: architecture and simulation results

Abstract: A data-aided frequency and symbol synchronization scheme for M-QAM OFDM signals is suggested. At first, the phase discriminator (PD) and frequency discriminator (FD) for, respectively, the symbol and frequency synchronization loop are described. Second, the transfer function and design parameters of the loop filters are provided. The acquisition and tracking performance of the synchronization system are evaluated using simulation for a 4-PSK signal constellation. The cases of additive white Gaussian noise (AWGN) and frequency and time selective multipath Rayleigh channels are separately tested.

A 1.8 GHz highly-tunable low-phase-noise CMOS VCO

Abstract: A 1.8 GHz fully integrated Voltage Controlled Oscillator (VCO) is presented. Through inductor optimization, the phase noise is as low as -127.5 dBc/Hz at 600 kHz and -142.5 dBc/Hz at 3 MHz. A 28% wide tuning range is achieved with a 1.8 V power supply. The VCO exceeds the DCS-1800 phase noise requirements with at least 4 dB over the whole DCS-1800 frequency band. The VCO is implemented in a 2-metal layer, 0.25 /spl mu/m standard CMOS technology, using no external components nor additional processing steps.

A fully-monolithic SiGe differential voltage-controlled oscillator for 5 GHz wireless applications

Abstract: A fully integrated and differential SiGe VCO was designed for 5 GHz wireless applications. The measured phase noise is -98 dBc/Hz at 100 kHz offset off the 5 GHz carrier. It has a tuning range of 12.3% with a control voltage from 0 to 3 V, and a figure of merit of more than -180 dBc/Hz, The current drawn from 3 V is 5 mA for the core and 2.2 mA for the output buffers.

VCO gain self-calibration for low voltage phase lock-loop applications

Abstract: A phase-locked loop (PLL) circuit having a voltage-controlled oscillator (VCO) is automatically calibrated for VCO center frequency and VCO gain during power up or responsive to a calibration signal. The VCO has several input voltage versus output frequency operating curves. During a calibration phase, proper VCO center frequency is selected by selecting one of the operating curves. VCO gain is then determined using the selected VCO operating curve. If the value of VCO gain is not within predetermined limits, VCO gain is adjusted accordingly, and the process of selecting a VCO operating curve and determining VCO gain is repeated.

A packaged 1.1-GHz CMOS VCO with phase noise of -126 dBc/Hz at a 600-kHz offset

Abstract: A packaged 1.1-GHz CMOS voltage-controlled oscillator (VCO) with measured phase noise of -92, -112, and -126 dBc/Hz at 10-, 100-, and 600-kHz offsets is demonstrated. According to J. Craninekx et al. (1997), these satisfy the GSM requirements. The extrapolated phase noise at a 3 MHz offset is -140 dBc/Hz. The power consumption is 6.8 and 12.7 mW at V/sub DD/=1.5 and 2.7 V, respectively. The VCO is implemented in a low-cost 0.8-/spl mu/m foundry CMOS process, which uses p+ substrates with a p-epitaxial layer. Buried channel PMOS transistors are exclusively used for lower 1/f noise. The inductors for the LC tanks are implemented using a series combination of an on-chip spiral inductor, four bond wires, and two package leads to increase Q. This technique requires no extra board space beyond that needed for the additional package leads.

Compact InP-based HBT VCOs with a wide tuning range at W- and D-band

Abstract: Compact monolithic integrated differential voltage-controlled oscillators (VCOs) operating in W-band were realized using InP-based heterojunction bipolar transistors (HBTs). The oscillators, with a total chip size of 0.6 by 0.35 mm/sup 2/, are based on a balanced Colpitts-type topology with a coplanar transmission-line resonator. By varying the voltage across the base-collector junction of the HBT in the current mirror and by changing the current in the VCO, the oscillation frequency can be tuned between 84 and 106 GHz. At 100 GHz, a differential voltage swing of 400 mV is obtained, which should be sufficient to drive 100 Gb/s digital logic. By combining the balanced outputs of a similar differential VCO in a push-push configuration, a compact source with close to -10 dBm output power and a tuning range between 138 and 150 GHz is obtained.