Showing papers on "Voltage-controlled oscillator published in 2001"

A filtering technique to lower LC oscillator phase noise

Abstract: Based on a physical understanding of phase-noise mechanisms, a passive LC filter is found to lower the phase-noise factor in a differential oscillator to its fundamental minimum. Three fully integrated LC voltage-controlled oscillators (VCOs) serve as a proof of concept. Two 1.1-GHz VCOs achieve -153 dBc/Hz at 3 MHz offset, biased at 3.7 mA from 2.5 V. A 2.1-GHz VCO achieves -148 dBc/Hz at 15 MHz offset, taking 4 mA from a 2.7-V supply. All oscillators use fully integrated resonators, and the first two exceed discrete transistor modules in figure of merit. Practical aspects and repercussions of the technique are discussed.

Concepts and methods in optimization of integrated LC VCOs

Abstract: Underlying physical mechanisms controlling the noise properties of oscillators are studied. This treatment shows the importance of inductance selection for oscillator noise optimization. A design strategy centered around an inductance selection scheme is executed using a practical graphical optimization method to optimize phase noise subject to design constraints such as power dissipation, tank amplitude, tuning range, startup condition, and diameters of spiral inductors. The optimization technique is demonstrated through a design example, leading to a 2.4-GHz fully integrated, LC voltage-controlled oscillator (VCO) implemented using 0.35-/spl mu/m MOS transistors. The measured phase-noise values are -121, -117, and -115 dBc/Hz at 600-kHz offset from 1.91, 2.03, and 2.60-GHz carriers, respectively. The VCO dissipates 4 mA from a 2.5-V supply voltage. The inversion mode MOSCAP tuning is used to achieve 26% of tuning range. Two figures of merit for performance comparison of various oscillators are introduced and used to compare this work to previously reported results.

A 2.4 GHz CMOS transceiver for Bluetooth

Abstract: A fully integrated CMOS transceiver tuned to 2.4 GHz consumes 46 mA in receive mode and 47 mA in transmit mode from a 2.7-V supply. It includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), power amplifier, and demodulator. The receiver uses a low-IF architecture for higher level of integration and lower power consumption. It achieves a sensitivity of -82 dBm at 0.1% BER, and a third-order input intercept point (IIP3) of -7 dBm. The direct-conversion transmitter delivers a GFSK modulated spectrum at a nominal output power of 4 dBm. The on-chip voltage controlled oscillator has a close-in phase-noise of -120 dBc/Hz at 3-MHz offset.

A 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator

Abstract: A 900-MHz two-stage CMOS voltage-controlled ring oscillator (VCO) with good phase-noise performance is presented. Implemented in a 0.5-/spl mu/m CMOS technology and at 2.5-V supply voltage, the VCO has a wide operating frequency range from 661.5 MHz to 1.27 GHz with a peak VCO gain (K/sub VCO/) of -630 MHz/V. At 900 MHz, the phase noise of the VCO is -105.5 dBc/Hz at 600-kHz frequency offset with low power consumption of 15.4 mW. The gain and phase mismatches are less than 0.25 dB and 0.5/spl deg/, respectively, which corresponds to an image rejection of better than 31 dB. The chip area is only 125/spl times/102 /spl mu/m/sup 2/.

A 1.25-GHz 0.35-/spl mu/m monolithic CMOS PLL based on a multiphase ring oscillator

Abstract: A general ring oscillator topology for multiphase outputs is presented and analyzed. The topology uses the interpolating inverter stages to construct fast subfeedback loops for long chain rings to obtain both multiphase outputs and higher speed operation. There exists an optimum number of inverter stages inside a subfeedback loop which gives the highest oscillation frequency. A fully integrated 1.25-GHz 0.35-/spl mu/m CMOS phase-locked-loop clock generator that incorporates the proposed voltage-controlled oscillator topology was designed and implemented for a data transceiver. It provides eight-phase outputs and achieves RMS tracking jitter of 11 ps from a 3.3-V power supply.

Fractional-order Wien-bridge oscillator

Abstract: The classical Wien-bridge sinusoidal oscillator is studied, when both of the capacitors of the oscillator acquire a fractional order. Accordingly, the Wien oscillator is described by a set of fractional-order nonlinear differential equations. It is shown that sinusoidal oscillations are preserved but the phase-shift between the waveforms of the two state variables and the frequency of oscillation both depend on the fractional-order, leading to a significant advantage over the integer-type Wien oscillator. Findings are validated via numerical simulations.

A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop

Abstract: A 900-MHz phase-locked loop frequency synthesizer implemented in a 0.6-/spl mu/m CMOS technology is developed for the wireless integrated network sensors applications. It incorporates an automatic switched-capacitor (SC) discrete-tuning loop to extend the overall frequency tuning range to 20%, while the VCO gain (K/sub VCO/) resulting from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V in order to improve the reference spurs and noise performance. This frequency synthesizer achieves a phase noise of -102 dBc/Hz at 100 kHz offset frequency and reference spurs below -55 dBc. The synthesizer, including an on-chip VCO, dissipates only 2.5 mA from a 3-V supply.

A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching

Abstract: This paper describes a 1.8-GHz self-calibrated phase-locked loop (PLL) implemented in 0.35-/spl mu/m CMOS technology. The PLL operates as an edge-combining type fractional-N frequency synthesizer using multiphase clock signals from a ring-type voltage-controlled oscillator (VCO). A self-calibration circuit in the PLL continuously adjusts delay mismatches among delay cells in the ring oscillator, eliminating the fractional spur commonly found in an edge-combing fractional divider due to the delay mismatches. With the calibration loop, the fractional spurs caused by the delay mismatches are reduced to -55 dBc, and the corresponding maximum phase offsets between the multiphase signals is less than 0.20. The frequency synthesizer PLL operates from 1.7 to 1.9 GHz and the closed-loop phase noise is -105 dBc/Hz at 100-kHz offset from the carrier. The overall circuit consumes 20 mA from a 3.0-V power supply.

Demonstration of a switched resonator concept in a dual-band monolithic CMOS LC-tuned VCO

Abstract: A switched resonator concept which allows better trade-off between phase noise and power consumption is demonstrated using a dual band VCO. The dual-band VCO operates near 900 MHz and 1.8 GHz with phase noise of -125 and 123 dBc/Hz at a 600-KHz offset and 16-mW power consumption. Compared to a single band 1.8 GHz VCO, the dual-band VCO has almost the same phase noise and power consumption.

Analog frequency modulation detector for dynamic force microscopy

Abstract: A new analog frequency modulation (FM) detector (demodulator) for dynamic force microscopy (DFM) is presented. The detector is designed for DFM by utilizing the FM detection method where the resonance frequency shift of the force sensor is kept constant to regulate the distance between a tip and a sample surface. The FM detector employs a phase-locked loop (PLL) circuit using a voltage-controlled crystal oscillator (VCXO) so that the thermal drift of the output signal is negligibly reduced. The PLL is used together with a frequency conversion (heterodyne) circuit allowing the FM detector to be used for a wide variety of force sensors with the resonance frequency ranging from 10 kHz to 10 MHz. The minimum detectable frequency shift was as small as 0.1 Hz at the detection bandwidth of 1 kHz. The detector can track a resonance frequency shift as large as 1 kHz. We also present some experimental results including the observations of the Si(111)-7×7 reconstructed surface and fullerene molecules deposited on the surface by DFM using this FM detector.

Fully integrated 5.35-GHz CMOS VCOs and prescalers

Abstract: Two 5.35-GHz monolithic voltage-controlled oscillators (VCOs) and two prescalers have been fabricated in a digital 0.25-/spl mu/m CMOS process. One VCO uses p/sup +//n-well diodes, while the other uses MOS varactors, Q of 57 at 5.5 GHz and 0 V bias (low-Q condition) for a p/sup +//n-well varactor has been achieved. For an MOS varactor, it is possible to achieve a quality factor of 140 at 5.5 GHz. The tuning ranges of the VCOs are >310 MHz, and their phase noise is <-116.5 dBc/Hz at a 1-MHz offset while consuming /spl sim/7 mW power at V/sub DD/=1.5 V. The low phase noise is achieved by using only PMOS transistors in the VCO core and by optimizing the resonator layout. The prescalers utilize a variation of the source-coupled logic. The power consumption is 4.1 mW at 1.5-V V/sub DD/ and 5.4 GHz. By widening the transistors in the first three divide-by-two stages, the maximum operating frequency is increased to 9.96 GHz at V/sub DD/=2.5 V.

Digital PLL (phase-locked loop) frequency synthesizer

Abstract: The circuit compensates for phase error in the case of fractional-N-based PLL frequency synthesizers. All required actuating and reference signals are derived from the VCO frequency of the voltage-controlled oscillator by using an auxiliary phase-locked loop. The circuit is specifically applicable for HF-PLL frequency synthesizers using integrated circuit technology.

Offset phase locking of Er,Yb:glass laser eigenstates for RF photonics applications

Abstract: An optical source of microwaves with very low phase noise for communications and radar systems is realized and tested. It is obtained by dual-frequency operation of a diode pumped Er,Yb:glass laser. An electrooptic crystal inserted inside the resonator permits both to tune the frequency difference between orthogonally polarized eigenstates, and to turn the laser into a voltage controlled oscillator. An optical phase-locked loop is then implemented in the GHz range, resulting in a measured instrument limited 3 dB-linewidth of 10 Hz. The phase noise is shown to be -100 dBc/Hz at 10-kHz offset.

A 4-GHz clock system for a high-performance system-on-a-chip design

Abstract: A digital system's clocks must have not only low jitter, but also well-controlled duty cycles in order to facilitate versatile clocking techniques. Power-supply noise is often the most common and dominant source of jitter on a phase-locked loop's (PLL) output clock. Jitter can be minimized by regulating the supply to the PLL's noise-sensitive analog circuit blocks in order to filter out supply noise. This paper introduces a PLL-based clock generator intended for use in a high-speed highly integrated system-on-a-chip design. The generator produces clocks with accurate duty cycles and phase relationships by means of a high-speed divider design. The PLL also achieves a power-supply rejection ratio (PSRR) greater than 40 dB while operating at frequencies exceeding 4 GHz. The high level of noise rejection exceeds that of earlier designs by using a combination of both passive and active filtering of the PLL's analog supply voltage. The PLL system has been integrated in a 0.15-/spl mu/m single-poly 5-metal digital CMOS technology. The measured performance indicates that at a 4-GHz output frequency the circuit achieves a PSRR greater than 40 dB. The peak cycle-to-cycle jitter is 25 ps at 700 MHz and a 2.8-GHz VCO frequency with a 500-mV step on the regulator's 3.3-V supply. The total power dissipated by the prototype is 130 mW and its active area is 1.48/spl times/1.00 mm/sup 2/.

Phase controlled oscillator

Abstract: An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.

A digitally controlled phase-locked loop with a digital phase-frequency detector for fast acquisition

Abstract: A digitally controlled phase-locked loop (DCPLL) that achieves fast acquisition by employing a digital phase-frequency detector (DPFD) and a variable loop gain scheme was developed for an advanced clock synthesizer and was fabricated in a 3.3-V 0.6-/spl mu/m CMOS process. The DPFD was developed to measure the frequency difference and to generate digital outputs corresponding to the difference. Using these features, the DCPLL achieves ideally one-cycle frequency acquisition when programmed with an appropriate gain. The experimental results show that the fabricated DCPLL exhibits three-cycle and one-cycle frequency acquisitions, when locking to 400 MHz (VCO at 800 MHz) and 200 MHz (VCO at 400 MHz), respectively.

Circuit Design for RF Transceivers

Abstract: 1. RF Design: Concepts and Technology 1.1 RF Specifications 1.1.1 Gain 1.1.2 Noise 1.1.3 Non-Linearity 1.1.4 Sensitivity 1.2 RF Device technology 1.2.1 Characterization and Modeling, Modeling, Cut-off Frequency, Maximum Oscillation Frequency, Input Limited Frequency, Output Limited Frequency, Maximum Available Bandwidth 1.2.2 Technology Choice, Double Poly Devices, Silicon-on-Anything, Comparison, SiGe Bipolar Technology, RF CMOS (updated for newer processes) 1.3 Passives 1.3.1 Resistors 1.3.2 Capacitors (updated for different layouts) 1.3.3 Planar Monolithic Inductors (updated as relation to newer processes) References (updated) 2. Antennas, Interface and substrate 2.1 Antennas 2.2 Bond wires 2.3 Transmission Lines 2.3.1 General Theory 2.3.2 Impedance Matching using Transmission Lines 2.3.3 Microstrip Lines and coplanar Lines 2.4 Bond Pads and ESD Devices 2.4.1 Bond Pads 2.4.2 ESD Devices, ggNMOST ESD Device, pn and np-diode ESD Device (updated for newer processes and detailed scaling effects) 2.5 Substrate 2.5.1 Substrate bounces 2.5.2 Design Techniques to Reduce the substrate bounce References (updated) 3. Low Noise Amplifiers 3.1 Specifications 3.2 Bipolar LNA designs 3.2.1 DCS applications in SOA, Design of the LNA, Measurements 3.2.2 Broadband LNA (new) 3.3 CMOS LNA Design 3.3.1 Single Transistor LNA, Design Steps, Simulation and Measurements 3.3.2 Classical LNA Design, The Design, Measurement Results 3.3.3 Broadband LNA (new) 3.4 Evaluation References (updated) 4. Mixers 4.1 Specification 4.2 Bipolar Mixer Design 4.3 CMOS mixers 4.3.1 Active CMOS mixer 4.3.2 Passive CMOS mixer, 1/f-Noise in mixer transistors, 1/f-Noise due to IF amplifier, 1/f-noise due to Switched-Capacitor Behavior 4.3.3 Concluding remarks References (Updated) 5. Case study Receiver front-ends (new) 5.1 Bluetooth (new) 5.2 IEEE 802.11a Standard (new) 6. RF Power Amplifier 6.1 Specification 6.1.1 Efficiency 6.1.2 Generic Amplifier Classes 6.1.3 Heating 6.1.4 Linearity 6.1.5 Ruggedness 6.2 Bipolar PA design 6.3 CMOS PA Design 6.4 Linearization Principles 6.4.1 Predistortion Technique 6.4.2 Phase-Correcting feedback 6.4.3 Envelope Elimination and Restoration (EER) 6.4.4 Cartesian Feedback 6.5 Case study: Bluetooth PA (new) References (updated) Note: Oscillator chapter: errors removed and updated throughout, sub-section headings probably quite similar but to be defined 7. Oscillators 7.1 Introduction 7.2 Specifications 7.3 LC oscillator 7.4 Ring oscillators 7.5 Phase noise modelling and simulation (new) 7.6 Typical oscillator performance (new) 7.7 Oscillator case studies (new), Wide range oscillators for mobile applications, Oscillators for ultra low-power wireless links, 10GHz CMOS VCO for WLAN, 10GHz QuBIC VCO for Satellite References (updated) 8. Frequency Synthesizers 8.1 Introduction 8.2 Integer-N PLL Architecture 8.3 Tuning System Specifications 8.3.1 Tuning Range 8.3.2

Automatic gain control for a voltage controlled oscillator

Abstract: A novel circuit topology which provides for the digital automatic gain control of a VCO is disclosed. The topology of the VCO is based on the negative transconductance oscillator due to its intrinsically simple biasing scheme. A system parameter sensitive to the performance level of the VCO is firstly measured. A digital control signal is then generated in response to the measured system parameter. The biasing current provided by the tail circuit of the VCO is adjusted based on the value of the digital control signal. In this way, the biasing current of the VCO may be adjusted to an optimal value for all frequencies of operation. The automatic control aspects of the present invention is useful in monolithic implementations since it automatically compensates for variations in load resistance, process parameters and component tolerances without requiring expensive manual adjustments at the board level.

PLL circuit, data detection circuit and disk apparatus

Abstract: A PLL circuit is disclosed which extracts phase difference information of a high S/N ratio from a readout signal uses the phase difference information for PLL control. An A/D converter samples the input signal to produce a digital signal. A pattern string detector identifies a type of an input pattern string formed from a plurality of successive sample values successively outputted from the A/D converter and outputs pattern string identification information which indicates an identification result. A phase difference generator outputs phase difference information which indicates a phase error of the output of the A/D converter based on the pattern string identification information and the output of the A/D converter. A loop filter, a D/A converter and a voltage controlled oscillator generate a clock signal from the phase difference information to control the sampling timing of the A/D converter.

New frequency-locked loop based on CMOS frequency-to-voltage converter: design and implementation

Abstract: In this paper, we describe the architecture of a new CMOS fully integrated frequency-locked loop (FLL). The proposed FLL contains a frequency-to-voltage converter (FVC), an operational amplifier (opamp) and a differential voltage-controlled oscillator (VCO). The operation of the proposed circuit is based on frequency comparison of reference and feedback signals. The architecture of the FVC is built upon capacitor charge redistribution principle, whereas the architecture of the VCO is based on differential delay cells in order to minimize the effect of the power supply and the substrate noise. Simulation carried out with HSpice using the CMOS 0.35-/spl mu/m process shows that the FLL is very fast and operates over a wide frequency range. Two versions of the FLL are reported; the basic architecture could show a static offset due to the two employed FVCs. To alleviate this effect, a second version is proposed to completely eliminate the offset. The area of the proposed FLL is very small, and the design could be easily integrated in the same die together with other analog, digital and mixed-signal blocks. A functional test of five samples of a first version of this FLL proved that the proposed FLL works as expected from simulation results. Examples of the application of the proposed FLL are a high-precision VCO and a frequency synthesizer with true-fractional multiplication and division that does not require binary frequency dividers.

Phase-locked loop employing programmable tapped-delay-line oscillator

Abstract: A phase-locked loop (PLL) having a wide range of oscillator output frequencies and a wide range of loop divider values is realizable in integrated form because the total capacitance of its loop filter is small. The PLL includes a first phase detector, a second phase detector, a programmable tapped-delay-line oscillator, a divide-by-M loop divider, and a programmable on-chip loop filter. The programmable filter is programmed to realize one of many loop filters. In a first step, oscillator output is fed back via the loop divider to the first phase detector. Oscillator frequency is decremented by changing tap selection inside the oscillator until the first phase detector determines that the frequency of the signal fed back via the loop divider (divide-by-M) is smaller than the frequency of an input signal. The tap control at which this frequency lock condition occurred, along with value M, is then used to determine which of the many loop filters will be used in a phase lock step. The programmable loop filter is controlled to realize the selected loop filter and the selected loop filter is switched into a control loop involving the second phase detector. The control loop controls the oscillator to achieve phase lock by varying a supply voltage supplied to the oscillator.

A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop

Abstract: The automatic amplitude control (AAC) loop is an indispensable element for the practical realization of VCOs embedded in a complete transceiver. Its noise however can unacceptably degrade the single-sideband-to-carrier ratio (SSCR) performance of the oscillator, this problem being even exacerbated in low-voltage circuits. This paper addresses the design issues of a low-voltage low-noise differential LC-VCO with AAC, tunable within a 2.3-2.8-GHz frequency range, fully integrated in bipolar technology with 2-V power supply. First, the mechanisms through which the AAC noise affects the output phase are identified as the poor indirect stability and the AM-to-PM conversion due to the varactors. The effect of the AAC noise is discussed and substantially reduced with suitable design choices. We show that the achievable noise-to-signal ratio is bounded by the shot noise coming from the bias source of the differential oscillator, an intrinsic limit set by the low supply voltage which does not allow for degeneration of the tail transistor. Second, the design of the AAC is discussed. A large gain-bandwidth product (GBWP), about 100 MHz, has been implemented in order to correct for the fast oscillation amplitude variations and reduce the effect of the ground line disturbances. The expected value of the phase noise level, SSCR at 100 kHz =-104 dBc/Hz, is tightly matched by the experimental results. The core oscillator dissipates 7 mA, while less than 600 /spl mu/A are drawn by the AAC circuit.

Design, fabrication, and application of precise SAW delay lines used in an FMCW radar system

Abstract: An inexpensive frequency-modulated continuous-wave (FMCW) radar system is presented in this paper, which, nevertheless, meets all industrial requirements. The FMCW radar uses a low-cost nonlinear voltage-controlled oscillator (VCO), operating at an IF of 2.45 GHz to generate the frequency modulation of the radar system. This VCO signal is applied twice, first to generate the radar transmitter signal at 24 GHz, and then it is fed to a surface acoustic wave (SAW) delay line. The SAW delay line generates a fixed delay time, which corresponds with a fixed radar distance. Thus, all systematic nonlinearities and stochastic phase errors of the FMCW system can be monitored and, afterwards, can be compensated for in real time. This linearization technique leads to a significant enhancement in dynamic range for a FMCW radar system. For this FMCW system, SAW delay lines with a linear phase characteristic have been designed using a linear optimization program. The delay line consists of two chirped and weighted interdigital transducers. For high volume, low-cost, and high-yield production of the required SAW structures, with linewidths down to 0.3 /spl mu/m, technological improvements had to be achieved, especially in photolithography. Based on these design and fabrication techniques, delay lines at 2.45 GHz operating at the fundamental and third harmonic with bandwidths up to 800 MHz have been realized.

A 9.8-11.5 GHz quadrature ring oscillator for optical receivers

Abstract: This paper describes a quadrature ring oscillator that is tunable from 9.8 to 11.5 GHz in a 30-GHz f/sub T/ BiCMOS technology. The ring oscillator can be used in advanced data clock recovery architectures in optical receivers. The circuit implementation of the oscillator uses transistors as active inductances. Isolation between the oscillator and cascaded circuits, such as buffers and flip-flops, is improved by utilizing the active inductances in a cascode configuration. Carrier to noise ratios better than 94 dBc/Hz at 2-MHz offset are measured with 75-mW dissipation and 2.7-V supply voltage. The evolution in two-stage ring oscillator topologies, leading to the realized design, is discussed in detail on the circuit level.

A 900 MHz dual conversion low-IF GSM receiver in 0.35 /spl mu/m CMOS

Abstract: A low-power fully integrated GSM receiver is developed in 0.35-/spl mu/m CMOS. This receiver uses dual conversion with a low IF of 140 kHz. This arrangement lessens the impact of the flicker noise. The first IF of 190 MHz best tolerates blocking signals. The receiver includes all of the circuits for analog channel selection, image rejection, and more than 100-dB controllable gain. The receiver alone consumes 22 mA from a 2.5-V supply, to give a noise figure of 5 dB, and input IP3 of -16 dBm. A single frequency synthesizer generates both LO frequencies. The integrated VCO with on-chip resonator and buffers consume another 8 mA, and meets GSM phase-noise specifications.

Low-phase-noise LC quadrature VCO using coupled tank resonators in a ring structure

Abstract: The concept of coupled resonators is employed in a ring VCO structure to reduce the phase noise. This architecture allows the design of low-phase-noise voltage controlled oscillators (VCOs) using integrated low-Q inductors. Quadrature differential outputs are also realized in this design. Two monolithic LC tanks are coupled together to implement a transimpedance resonator with an effective Q close to twice that of a single tank. In addition, the coupled tank's transimpedance resonator provides 90/spl deg/ phase shift. Four such stages are cascaded in a ring structure to provide I-Q differential outputs, and to further reduce the phase noise. A prototype of the VCO is built in a 0.35-/spl mu/m CMOS technology. The measured phase noise is -122 dBc/Hz at 600-kHz offset from 1.93 GHz. The VCO draws 9.2 mA from a 3-V supply, and occupies a chip area of 1.1/spl times/1.1 mm/sup 2/.

A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications

Abstract: A 5-GHz, fully monolithic voltage-controlled oscillator (VCO) for Bluetooth wireless transceivers is demonstrated in a 0.25 /spl mu/m CMOS technology using accumulation mode varactors and spiral inductors. An 18% tuning range was measured for only 2.5 V tuning-voltage variation. The phase noise was -94 dBc/Hz at 100 kHz frequency offset with 40 kHz 1/f/sup 3/ corner frequency. These low values are limited by the up-conversion of flicker noise due to varactor amplitude-to-frequency conversion and to the modulation of the varactor bias point. This explanation is verified by simulations and measurements. The circuit draws 5.5 mA from a 2.5 V power supply.

A 0.6-2.5 GBaud CMOS tracked 3/spl times/ oversampling transceiver with dead-zone phase detection for robust clock/data recovery

Abstract: For generation of the multiphase clocks for a serializer, a wide-range multiphase delay-locked loop (DLL) is used in the transmitter to avoid the detrimental characteristics of a phase-locked loop (PLL), such as jitter peaking and accumulated phase error. A tracked 3 /spl times/ oversampling technique with dead-zone phase detection is incorporated in the receiver for robust clock/data recovery in the presence of excessive jitter and intersymbol interference (ISI). Due to the dead-zone phase detection, phase adjustment is performed only on the tail portions of the transition histogram in the received data eye, thereby exhibiting wide pumping-current range, large jitter tolerance, and small phase error. A voltage-controlled oscillator (VCO), based on a folded starved inverter, shows about 50% less jitter than one with replica bias. The transceiver, implemented in 0.25-/spl mu/m CMOS technology, operates at 2.5 GBaud over a 10-m 150-/spl Omega/ STP cable and at 1.25 GBaud over a 25-m cable with a bit error rate (BER) of less than 10/sup -13/.

Fast coarse tuning control for pll frequency synthesizer

Abstract: The VCO of a synthesizer operates with a coarse tuning and a fine tuning. During the coarse tuning, a binary search method is used to match the VCO frequency to one of a finite number of discrete reference frequencies. The coarse tuning operates without frequency division and phase comparison in a closed feedback loop, thereby speeding up the settling time and increasing the lock-in range. The fine tuning operates as a conventional analog PLL.

PLL/DLL dual loop data synchronization

Abstract: A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.