Showing papers on "Voltage-controlled oscillator published in 2002"

A noise-shifting differential Colpitts VCO

Abstract: A novel noise-shifting differential Colpitts VCO is presented. It uses current switching to lower phase noise by cyclostationary noise alignment and improve the start-up condition. A design strategy is also devised to enhance the phase noise performance of quadrature coupled oscillators. Two integrated VCOs are presented as design examples.

Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion

Abstract: The tuning curve of an LC-tuned voltage-controlled oscillator (VCO) substantially deviates from the ideal curve 1//spl radic/(LC(V)) when a varactor with an abrupt C(V) characteristic is adopted and the full oscillator swing is applied directly across the varactor. The tuning curve becomes strongly dependent on the oscillator bias current. As a result, the practical tuning range is reduced and the upconverted flicker noise of the bias current dominates the 1/f/sup 3/ close-in phase noise, even if the waveform symmetry has been assured. A first-order estimation of the tuning curve for MOS-varactor-tuned VCOs is provided. Based on this result, a simplified phase-noise model for double cross-coupled VCOs is derived. This model can be easily adapted to cover other LC-tuned oscillator topologies. The theoretical analyses are experimentally validated with a 0.25 /spl mu/m CMOS fully integrated VCO for 5 GHz wireless LAN receivers. By eliminating the bias current generator in a second oscillator, the close-in phase noise improves by 10 dB and features -70 dBc/Hz at 10 kHz offset. The 1/f/sup 2/ noise is -132 dBc/Hz at 3 MHz offset. The tuning range spans from 4.6 to 5.7 GHz (21%) and the current consumption is 2.9 mA.

A multiple-crystal interface PLL with VCO realignment to reduce phase noise

Abstract: An enhancement to a conventional integer-N phase-locked loop (PLL) is introduced, analyzed, and demonstrated experimentally to significantly reduce voltage-controlled oscillator (VCO) phase noise. The enhancement, which involves periodically injection locking the VCO to a buffered version of the reference, has the effect of widening the PLL bandwidth and reducing the overall phase noise. It is demonstrated in a 3-V 6.8-mW CMOS reference PLL with a ring VCO capable of converting most of the popular crystal reference frequencies to a 96-MHz RF PLL reference and baseband clock for a direct conversion Bluetooth wireless LAN. The peak in-band phase noise at an offset of 20 kHz is -102 dBc/Hz with the technique enabled and -92 dBc/Hz with the technique disabled. A theoretical analysis is presented and shown to be in close agreement with the measured results.

A single-chip quad-band (850/900/1800/1900 MHz) direct conversion GSM/GPRS RF transceiver with integrated VCOs and fractional-n synthesizer

Abstract: Recent trends in the integration of entire systems on-chip have spurred the development of homodyne radios as alternatives to the more mature yet harder to integrate superheterodyne architectures. This paper presents a monolithic device that integrates all of the functions necessary to implement a multiband homodyne global system for mobile telecommunications (GSM) radio except for the power amplifier (PA) and radio frequency (RF) passives. The single BiCMOS chip includes a quad-band direct conversion receiver that down converts RF to quadrature analog baseband. The front-end circuitry is followed by a low-DC-offset, high-dynamic-range, analog I/Q baseband chain. The transmit section is comprised of a quad-band up-conversion transmit phase-locked loop (PLL) including on chip transmit voltage-controlled oscillators (VCOs). The stringent GSM receive band phase noise specifications are met without the use of surface acoustic wave filters. A single /spl Sigma//spl Delta/ fractional-N synthesizer locking a fully integrated ultrahigh frequency VCO generates the system local oscillator signal.

Noise analysis of phase-locked loops

Abstract: This work addresses the problem of noise analysis of phase-locked loops (PLLs). The problem is formulated as a stochastic differential equation and is solved in the presence of circuit white noise sources yielding the spectrum of the PLL output. Specifically, the effect of loop filter characteristics, phase-frequency detector, and phase noise of the open-loop voltage-controlled oscillator (VCO) on the PLL output spectrum is quantified. These results are derived using a full nonlinear analysis of the VCO in the feedback loop and cannot be predicted using traditional linear analyses or the phase noise analysis of open-loop oscillators. The computed spectrum matches well with measured results; specifically, the shape of the output spectrum matches very well with measured PLL output spectra reported in the literature for different kinds of loop filters and phase detectors. The PLL output spectrum computation only requires the phase noise of the VCO, loop filter and phase detector noise, phase detector gain, and loop filter transfer function and does not require the transient simulation of the entire PLL which can be very expensive. The noise analysis technique is illustrated with some examples.

Integrated VCO having an improved tuning range over process and temperature variations

Abstract: An integrated VCO having an improved tuning range over process and temperature variations. There is therefore provided in a present embodiment of the invention an integrated VCO. The VCO comprises, a substrate, a VCO tuning control circuit responsive to a VCO state variable that is disposed upon the substrate, and a VCO disposed upon the substrate, having a tuning control voltage input falling within a VCO tuning range for adjusting a VCO frequency output, and having its tuning range adjusted by the tuning control circuit in response to the VCO state variable.

A CMOS monolithic /spl Delta//spl Sigma/-controlled fractional-N frequency synthesizer for DCS-1800

Abstract: A monolithic 1.8-GHz /spl Delta//spl Sigma/-controlled fractional-N phase-locked loop (PLL) frequency synthesizer is implemented in a standard 0.25-/spl mu/m CMOS technology. The monolithic fourth-order type-II PLL integrates the digital synthesizer part together with a fully integrated LC VCO, a high-speed prescaler, and a 35-kHz dual-path loop filter on a die of only 2/spl times/2 mm/sup 2/. To investigate the influence of the /spl Delta//spl Sigma/ modulator on the synthesizer's spectral purity, a fast nonlinear analysis method is developed and experimentally verified. Nonlinear mixing in the phase-frequency detector (PFD) is identified as the main source of spectral pollution in /spl Delta//spl Sigma/ fractional-N synthesizers. The design of the zero-dead zone PFD and the dual charge pump is optimized toward linearity and spurious suppression. The frequency synthesizer consumes 35 mA from a single 2-V power supply. The measured phase noise is as low as -120 dBc/Hz at 600 kHz and -139 dBc/Hz at 3 MHz. The measured fractional spur level is less than -100 dBc, even for fractional frequencies close to integer multiples of the reference frequency, thereby satisfying the DCS-1800 spectral purity constraints.

Method and apparatus for controlling ultrasonic transducer

Abstract: Method and apparatus for implementing ultrasonic systems that maximize efficiency by dynamically detecting and maintaining peak operational resonance frequency. In one embodiment, the invention dynamically sweeps the output frequency range to locate the peak load current. The resonance frequency corresponding to the peak load current is used as a reference frequency in a control loop. The control loop includes a voltage-controlled oscillator (VCO) that is controlled by a loop controller and operates to lock onto the dynamically sensed reference frequency. In response to the VCO output, a pulse-width modulator (PWM) circuit drives a pair of switches that adjust transducer current to maintain the circuit locked on the resonance frequency at a substantially constant current.

Satellite positioning system receiver with reference oscillator circuit and methods therefor

Abstract: A method in a location enabled mobile wireless receiver having an oscillator, including determining a change in cellular network based frequency error of the oscillator (250), based on a difference (230) between a cellular network based frequency error of the oscillator and a reference cellular network based frequency error (210) of the oscillator, determining a first frequency error of the oscillator by summing (250) a reference satellite positioning system receiver based oscillator frequency error (220) with the change in cellular network based frequency error of the oscillator.

Communication semiconductor integrated circuit device and a wireless communication system

Abstract: In a communication semiconductor integrated circuit device using offset PLL architectures and including an oscillator circuit and a frequency divider circuit generating an intermediate frequency signal, the oscillator circuit includes an oscillator, a programmable frequency divider which frequency-divides the oscillation signal in accordance with frequency division information, a phase comparator detecting a phase difference between an output signal of the programmable frequency divider and a reference signal, and a frequency control unit for outputting a signal indicative of the phase difference and controlling the oscillation frequency of the oscillator, wherein a frequency division ratio generator circuit generates an integer part I and a fraction part F/G based on band information concerning the use frequency band and mode information along with channel information and for producing the frequency division ratio information to thereby give it to the programmable frequency divider.

Design of low-phase-noise CMOS ring oscillators

Abstract: This paper presents a framework for modeling the phase noise in complementary metal-oxide-semiconductor (CMOS) ring oscillators. The analysis considers both linear and nonlinear operations, and it includes both device noise and digital switching noise coupled through the power supply and substrate. In this paper, we show that fast rail-to-rail switching is required in order to achieve low phase noise. Further, flicker noise from the bias circuit can potentially dominate the phase noise at low offset frequencies. We define the effective Q factor for ring oscillators with large and nonlinear voltage swings and predict its increase for CMOS processes with smaller feature sizes. Our phase-noise analysis is validated via simulation and measurement results for ring oscillators fabricated in a number of CMOS processes.

A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop

Abstract: A 1.5-V 5.5-GHz fully integrated phase-locked loop (PLL) has been implemented in a 0.25-/spl mu/m foundry digital CMOS process. From a 5.5-GHz carrier, the in-band phase noise can be as low as -88 dBc/Hz at a 40-kHz offset, while the phase noise for the free-running VCO is -116 dBc/Hz at an 1-MHz offset. The VCO core current is 4.6 mA. The prescaler is implemented using a variation of the source-coupled logic (SCL) structure to reduce the switching noise, and thus to reduce the PLL side-band spurs. At -18 dBm signal power measured off chip, the switching noise coupled through substrate and metal interconnect generates spurs with power levels less than -99 dBm when the loop is open. A new charge-pump circuit is developed to reduce the current glitch at the output node. By incorporating a voltage doubler, the voltage dynamic range at the charge-pump output and thus the VCO control voltage range is increased from 1.3 to 2.6 V with immeasurable phase noise and spurious level degradation to the PLL. When the loop is closed, the power levels of side-band spurs at the offset frequency equal to the /spl sim/43-MHz reference frequency are < -69 dBc. The total power consumption of the PLL including that for the output buffers is /spl sim/23 mW.

OC-192 transmitter and receiver in standard 0.18-/spl mu/m CMOS

Abstract: This paper presents the first fully integrated SONET OC-192 transmitter and receiver fabricated in a standard 0.18-/spl mu/m CMOS process. The transmitter consists of an input data register, 16-b-wide first-in-first-out (FIFO) circuit, clock multiplier unit (CMU), and 16:1 multiplexer to give a 10-Gb/s serial output. The receiver integrates an input amplifier for 10-Gb/s data, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. An on-chip LC-type voltage-controlled oscillator (VCO) is employed by both the transmitter and receiver. The chipset operates at multiple data rates (9.95-10.71 Gb/s) with functionality compatible with the multisource agreement (MSA) for 10-Gb transponders. Both chips demonstrate SONET-compliant jitter characteristics. The transmitter 10.66-GHz output clock jitter is 0.065 UI/sub pp/ (unit interval, peak-to-peak) over a 50-kHz-80-MHz bandwidth. The receiver jitter tolerance is more than 0.4 UI/sub pp/ at high frequencies (4-80 MHz). A high level of integration and low-power consumption is achieved by using a standard CMOS process. The transmitter and receiver dissipate a total power of 1.32 W at 1.8 V and are packaged in a plastic ball grid array with a footprint of 11/spl times/11 mm/sup 2/.

A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

Abstract: A fully integrated CMOS frequency synthesizer for PCS- and cellular-CDMA systems is integrated in a 0.35-/spl mu/m CMOS technology. The proposed charge-averaging charge pump scheme suppresses fractional spurs to the level of noise, and the improved architecture of the dual-path loop filter makes it possible to implement a large time constant on a chip. With current-feedback bias and coarse tuning, a voltage-controlled oscillator (VCO) enables constant power and low gain of the VCO. Power dissipation is 60 mW with a 3.0-V supply. The proposed frequency synthesizer provides 10-kHz channel spacing with phase noise of -121 dBc/Hz in the PCS band and -127 dBc/Hz in the cellular band, both at 1-MHz offset frequency.

PLL Tracking Performance in the Presence of Oscillator Phase Noise

Abstract: The tracking performance of a Phase Lock Loop (PLL) is affected by the influence of several error sources. In addition to thermal noise and dynamic stress error, oscillator phase noise can cause significant phase jitter which degrades the tracking performance. Oscillator phase noise is usually caused by two different effects: Allan deviation phase noise is caused by frequency instabilities of the receiver's reference oscillator and the satellite's frequency standard. It can be termed as system-inherent phase noise and is relevant for both static and dynamic applications. “External” phase noise, however, is caused by vibration and is a major problem for dynamic applications. In the context of this paper, both types of phase noise will be modeled and the resulting integrals will be evaluated for PLLs up to the third order. Besides, phase jitter induced by thermal noise and signal dynamics will also be discussed, thus providing all necessary formulas for analyzing the performance of a phase lock loop in case of different forms of stress. Since the main focus is centered on the effects of oscillator phase noise, the overall PLL performance is graphically illustrated with and without consideration of oscillator phase noise. © 2002 Wiley Periodicals, Inc.

Up/down conversion circuitry for radio transceiver

Abstract: A multi-channel RF receiver uses an image rejection mixer (e.g. double quadrature mixer) in the IF down conversion stage for image side band rejection (whereby use of an IF narrow band filter for image rejection may be omitted if desired) and comprises a simplified frequency synthesizer which generates both a “wandering” IF oscillator frequency and an RF oscillator frequency for the up/down conversion stages (being, for down conversion, from RF to IF and from IF to base band. The IF used for a particular RF carrier (channel) is selected so as to be both an integer (N) sub-harmonic of that RF carrier and within the operating frequency band of the image rejection mixer. Advantageously, the synthesizer comprises only one loop and one VCO, wherein the IF oscillator signal is produced from the RF oscillator signal by means of a frequency divider.

Local oscillator leakage control in direct conversion processes

Abstract: A system and method for generating a local oscillator (LO) frequency in a zero intermediate frequency (IF) receiver or transmitter is presented. A signal is received from a voltage controlled oscillator (VCO). The signal has a VCO frequency. The VCO frequency is divided by a number N to produce a signal having a divided-down frequency. The signal having the VCO frequency is then mixed with the signal having the divided-down frequency to produce an output signal having an output frequency. Local oscillator leakage is reduced. Thus, the receiver or transmitter may operate in multiple wireless communication bands and modes and meet the associated specifications.

A compact LTCC-based Ku-band transmitter module

Abstract: Presents design, implementation, and measurement of a three-dimensional (3-D)-deployed RF front-end system-on-package (SOP) in a standard multi-layer low temperature co-fired ceramic (LTCC) technology. A compact 14 GHz GaAs MESFET-based transmitter module integrated with an embedded bandpass filter was built on LTCC 951AT tapes. The up-converter MMIC integrated with a voltage controlled oscillator (VCO) exhibits a measured up-conversion gain of 15 dB and an IIP3 of 15 dBm, while the power amplifier (PA) MMIC shows a measured gain of 31 dB and a 1-dB compression output power of 26 dBm at 14 GHz. Both MMICs were integrated on a compact LTCC module where an embedded front-end band pass filter (BPF) with a measured insertion loss of 3 dB at 14.25 GHz was integrated. The transmitter module is compact in size (400 /spl times/ 310 /spl times/ 35.2 mil/sup 3/), however it demonstrated an overall up-conversion gain of 41 dB, and available data rate of 32 Mbps with adjacent channel power ratio (ACPR) of 42 dB. These results suggest the feasibility of building highly SOP integrated RF front ends for microwave and millimeter wave applications.

Vco gain tracking for modulation gain setting calibration

Abstract: Voltage controlled oscillator (VCO) gain tracking is used for programming modulation gain settings to minimize modulation distortion in a low bandwidth phase locked loop of a mobile station (10). A synthesizer (20) generates a tuning voltage (Vt) for controlling a frequency of a voltage controlled oscillator (VCO) modulated radio frequency signal. A controller (22) outputs a modulation data signal and includes an analog to digital converter (72) for receiving the tuning voltage from the synthesizer (20) on a VCO feedback loop (70), a gain control lookup table (LUT) (76) for storing modulation gain setting calibration data for respective mobile station sub-bands, and a gain setting digital to analog converter (DAC) (78) for outputting a modulation gain control signal to the synthesizer (20). The modulation gain setting calibration data is calibrated using a one-time or continuous calibration methodology during, respectively, a background or normal mode of mobile station operation.

A 5.8 GHz fully integrated low power low phase noise CMOS LC VCO for WLAN applications

Abstract: A fully integrated low power and low phase noise 5.8 GHz VCO is designed and fabricated in standard 0.24 /spl mu/m single-poly, 5-metal digital CMOS process. The VCO-core draws 2 mA of current from a 2.5 V supply. Measured phase noise at 1 MHz offset from the center frequency is -112 dBc/Hz. It has a tuning range of 810 MHz with low phase noise performance throughout the tuning range. It meets the requirements for IEEE802.11a WLAN standard. Low power and low phase noise have been achieved simultaneously by the use of np complementary cross-coupled topology. The novel orientation of the inductor pair used in the design minimizes the effect of any unwanted common-mode magnetic coupling that may arise from other on-chip inductors in an integrated environment.

Low-jitter clock multiplication: a comparison between PLLs and DLLs

Abstract: This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage.

A low-noise transformer-based 1.7 GHz CMOS VCO

Abstract: A low-noise transformer-based 0.35 /spl mu/m CMOS VCO operates at 1.7 GHz. The VCO core consumes 4.5 mA from 2.5 V, and results in phase noise of -116, -137 and -142 dBc/Hz at 100 k, 600 k and 1 MHz from the carrier, respectively. The tuning range is 107 MHz for 0-2.5 V tuning voltage. The oscillator is based on a transformer-type resonator.

A low-phase-noise low-phase-error 1.8 GHz quadrature CMOS VCO

Abstract: A 1.8 GHz quadrature VCO in standard 0.35 /spl mu/m CMOS with three metal layers shows -140 dBc/Hz or less phase noise across an 18% tuning range, while drawing 25 mA from a 2 V power supply. The quadrature phase error between the VCO outputs is at most 0.25/spl deg/.

Digital baseband receiver in a multi-carrier power amplifier

Abstract: A power amplifier system and method for locating carrier frequencies across a frequency band, identifying the modulation format of each carrier, and locating and suppressing undesired intermodulation distortion (IMD) products generated by the power amplifier. The system includes an amplifier for amplifying RF carrier signals in a main signal path, a variable phase shifter and variable attenuator on a feed forward path, and a tunable receiver that digitizes a portion of the frequency band to baseband. The tunable receiver includes a tunable voltage controlled oscillator which provides an oscillating frequency to a mixer and is phase-locked to a highly stable reference oscillator. The mixer downconverts a desired RF based on the oscillating frequency to IF. A filter passes only a selected portion of the IF signals, and the filter has a passband sufficient to discern both narrowband and wideband carriers and their associated IMD products. Based on the locations of the carrier frequencies, a processing unit determines the IMD locations of the carrier frequencies, determines the IMD locations, and adjusts the variable phase shifter and variable attenuator on the feed forward path until the IMD products in the main signal path are suppressed below a desired threshold.

Phase synchronizing circuit

Abstract: An object of this invention is to provide a phase synchronizing circuit capable of automatically adjusting a VCO such that the VCO satisfies a predetermined frequency range even in a frequency range in which the VCO oscillates by a leak current generated if a low threshold process is applied. The phase synchronizing circuit is composed of a PLL consisting of a phase comparator, a charge pump, a loop filter, a VCO, and a divider, and a calibration circuit for automatically adjusting a frequency range of the VCO. Before a convergence operation is started, a switch is closed in response to a signal Rst of the calibration circuit such that an output of the loop filter is leveled to the ground and the PLL is set to be an open loop. A VCO output Fo is set at an upper limit frequency or a lower limit frequency in response to a Vcal signal, and its frequency is measured by comparing its period with a period of a reference signal Fr, and signals Hb, Lb used for adjusting the frequency of the VCO are updated. The signals Hb, Lb are updated until the VCO satisfies the predetermined frequency range, and subsequently their values are maintained. The switch opens in response to the signal Rst, and the PLL is changed over to a close loop to start phase synchronization.

Impedance tuning circuit

Abstract: A feedback system such as a phase locked loop (PLL) includes a second feedback loop which responds when a VCO control voltage is near either end of its range, by slowly adjusting additional tuning elements which control the VCO frequency. The second feedback loop is arranged to cause a slow enough change in the VCO frequency that the first traditional feedback loop adjusts the control voltage quickly enough in a direction toward its mid-range value to keep the VCO frequency substantially unchanged. The second feedback loop advantageously incorporates one or more digital control signals which preferably change no more than one bit at a time and with a controlled slow ramp rate. As a result, the PLL maintains phase accuracy so that the operation of the PLL, including subtle specifications such as input data jitter tolerance or output jitter generation when used for clock and data recovery applications, is not negatively impacted. An impedance tuning feedback system provides a resistance between two nodes which is proportional to a reference resistance, and preferably incorporates slow digital switching to result in near perturbation-free state changes over the tuning range of the resistance.

Control system with capacitive detector

Abstract: A capacitive sensor system for controlling operation of a device in response to a rate of change in capacitance due to motion of a proximate object includes at least two sense electrodes (14,16) disposed on a surface and a phase locked loop (12), including a voltage controlled oscillator (22) and a phase/frequency comparator (24), connected between the sense electrodes and an RC network (20) for providing an operating frequency to the sense electrodes. A circuit loop, including a reference oscillator (32), provides a fixed frequency references for the phase locked loop to follow and a phase delay circuit (34) connected between the phase/frequency comparator and the voltage controlled oscillator causes the voltage controlled oscillation to run ahead of the reference oscillator. A trigger circuit (30) provides a control output in response to a change in phase shift between the fixed frequency and the operating frequency.

QPSK and 16 QAM self-generating synchronous direct downconversion demodulator

Abstract: A system for recovering and demodulating a carrier includes a carrier recovery loop and a data detector. The carrier recovery loop receives the carrier as an input and produces a recovered carrier at a frequency approximately equal to that of the carrier. The carrier recovery loop includes a downconverting mixer, a ×5 multiplier, a ×4 multiplier, and a phase locked loop. The downconverting mixer receives the carrier input, and the phase locked loop provides a VCO reference frequency through the ×5 multiplier to the downconverting mixer, which provides a frequency shifted signal. The frequency shifted signal is passed through the ×4 multiplier as input to the phase locked loop. The data detector receives the carrier and the recovered carrier as inputs and uses the recovered carrier to demodulate the carrier and detect I channel data and Q channel data.

Voltage controlled ring oscillator with wide tuning range and fast voltage swing

Abstract: A new design of a voltage controlled ring oscillator is proposed. The proposed design allows an implementation of a low frequency ring oscillator using relatively small devices and less stages. A voltage controlled ring oscillator with tuning range from 40 Hz to 380 MHz is achieved using the proposed method. In addition, the proposed circuit enables the output voltage to swing faster than the conventional one.

A CMOS fully integrated 1 GHz and 2 GHz dual band VCO with a voltage controlled inductor

Abstract: A fully integrated voltage controlled oscillator with a wide tuning range from 978 MHz to 2010 MHz is presented. The LC-VCO was designed in INFINEON low-cost 0.25 µm 4 metal standard CMOS process, using an integrated fully symmetrical coil. The frequency of the presented LC-VCO is both capacitance- and inductance-controlled. A novel voltage controlled fully differential inductor is introduced. Testchip results using the inductance tuning to implement a dual band VCO are presented. At 1GHz the VCO consumes 7.5 mA from a 1.5 V supply voltage and features a measured phasenoise of -138 dBc/Hz at 3 MHz offer. At 2 GHz 9 mA from a 1.5 V supply is consumed and the VCO features a measured phasenoise of -132 dBc/Hz at 3 MHz offer.