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Showing papers on "Voltage-controlled oscillator published in 2003"


Journal ArticleDOI
TL;DR: In this article, a new concept for quadrature coupling of LC oscillators is introduced and demonstrated on a 5 GHz CMOS voltage-controlled oscillator. But the technique is limited to a single oscillator and it is not suitable for a large number of oscillators.
Abstract: A new concept for quadrature coupling of LC oscillators is introduced and demonstrated on a 5-GHz CMOS voltage-controlled oscillator (VCO). It uses the second harmonic of the outputs to couple the oscillators. The technique provides quadrature over a wide tuning range without introducing any increase in phase noise or power consumption. The VCO is tunable between 4.57 and 5.21 GHz and has a phase noise lower than -124 dBc/Hz at 1-MHz offset over the entire tuning range. The worst-case measured image rejection is 33 dB. The circuit draws 8.75 mA from a 2.5-V supply.

312 citations


Journal ArticleDOI
TL;DR: In this article, a low-cost microwave oscillator is proposed, which makes use of a substrate integrated waveguide (SIW) cavity that acts as a frequency selector as well as a feedback-coupling device.
Abstract: A topology is proposed for designing a low-cost microwave oscillator. This new feedback oscillator makes use of a substrate integrated waveguide (SIW) cavity that acts as a frequency selector as well as a feedback-coupling device. The oscillator is stabilized by using an injection-locking scheme. A 12.02-GHz oscillator prototype was designed. Experimental results for phase noise, locking range, and quality factor of the new circuit are presented. An external Q of 178 was measured.

246 citations


Journal ArticleDOI
TL;DR: In this article, a simple analysis relates the small-signal specification of a varactor's capacitance to an oscillator's tuning curve and explains how the varactor converts AM noise on the oscillation into FM, which is phase noise.
Abstract: A simple analysis relates the small-signal specification of a varactor's capacitance to an oscillator's tuning curve. The notion of an effective capacitance across the amplitude of oscillation is introduced. The analysis also explains how the varactor converts AM noise on the oscillation into FM, which is phase noise. The analysis is experimentally validated.

219 citations


Journal ArticleDOI
TL;DR: In this paper, a general design methodology of low-voltage wideband voltage-controlled oscillator (VCO) suitable for wireless LAN (WLAN) application is described, and the applications of high-quality passives for the resonator are introduced: a single-loop horseshoe inductor with Q > 20 between 2 and 5 GHz for good phase noise performance; and accumulation MOS (AMOS) varactors with C/sub max/C/sub min/ ratio of 6 to provide wide-band tuning capability at lowvoltage supply.
Abstract: In this paper, a general design methodology of low-voltage wide-band voltage-controlled oscillator (VCO) suitable for wireless LAN (WLAN) application is described. The applications of high-quality passives for the resonator are introduced: 1) a single-loop horseshoe inductor with Q > 20 between 2 and 5 GHz for good phase noise performance; and 2) accumulation MOS (AMOS) varactors with C/sub max//C/sub min/ ratio of 6 to provide wide-band tuning capability at low-voltage supply. The adverse effect of AMOS varactors due to high sensitivity is examined. Amendment using bandswitching topology is suggested, and a phase noise improvement of 7 dB is measured to prove the concept. The measured VCO operates on a 1-V supply with a wide tuning range of 58.7% between 3.0 and 5.6 GHz when tuned between /spl plusmn/0.7 V. The phase noise is -120 dBc/Hz at 3.0 GHz, and -114.5 dBc/Hz at 5.6 GHz, with the nominal power dissipation between 2 and 3 mW across the whole tuning range. The best phase noise at 1-MHz offset is -124 dBc/Hz at the frequency of 3 GHz, a supply voltage of 1.4 V, and power dissipation of 8.4 mW. When the supply is reduced to 0.83 V, the VCO dissipates less than 1 mW at 5.6 GHz. Using this design methodology, the feasibility of generating two local oscillator frequencies (2.4-GHz ISM and 5-GHz U-NII) for WLAN transceiver using a single VCO with only one monolithic inductor is demonstrated. The VCO is fabricated in a 0.13-/spl mu/m partially depleted silicon-on-insulator CMOS process.

211 citations


Journal ArticleDOI
TL;DR: In this paper, a second-order RF bandpass filter based on active inductor has been implemented in a 0.35 /spl mu/m CMOS process, which has 28dB spurious-free-dynamic-range (SFDR) and total current consumption (including buffer stage) is 17 mA with 2.7-V power supply.
Abstract: In this paper, a second-order RF bandpass filter based on active inductor has been implemented in a 0.35 /spl mu/m CMOS process. Issues related to the intrinsic quality factor and dynamic range of the CMOS active inductor are addressed. Tuned at 900 MHz with Q=40, the filter has 28-dB spurious-free-dynamic-range (SFDR) and total current consumption (including buffer stage) is 17 mA with 2.7-V power supply. Experimental results also show the possibility of using them to build higher order RF filter and voltage-controlled oscillator (VCO).

163 citations


Journal ArticleDOI
TL;DR: In this article, a SiGe bipolar production technology was used to design a low-cost differential circuit for millimeter-wave voltage-controlled oscillators (VCOs) with low phase noise and wide tuning range.
Abstract: Millimeter-wave voltage-controlled oscillators (VCOs) are presented which are fully integrated in a SiGe bipolar production technology. The low-cost differential circuits have been designed and optimized for low phase noise and wide tuning range. As an example, by varying the bias voltage of the on-chip varactor, the oscillation frequency can be changed from 36 to 46.9 GHz (i.e., by 26%). In this wide frequency range, phase noise between -107 and -110dBc/Hz at 1-MHz offset frequency and single-ended voltage swing of about 0.95V/sub pp/ /spl plusmn/10% (differential: 1.9V/sub pp/) were measured. The circuit consumes 280mW at -5.5-V supply voltage. The high oscillation frequency and low phase noise at wide tuning range are record values for fully integrated oscillators in Si-based technologies. The basic oscillator was then extended by a cascode stage as an output buffer. Now the VCO performance is no longer degraded if nonperfectly terminated transmission lines are driven. Thus, the chip can be mounted in a low-cost socket; however, at the cost of increased phase noise and power consumption.

161 citations


Journal ArticleDOI
TL;DR: In this article, the large-signal swing of the VCO output oscillation modulates the varactor capacitance in time, resulting in a VCO tuning curve that deviates from the dc tuning curve of the particular varactor structure.
Abstract: MOS varactors are used extensively as tunable elements in the tank circuits of RF voltage-controlled oscillators (VCOs) based on submicrometer CMOS technologies. MOS varactor topologies include conventional D = S = B connected, inversion-mode (I-MOS), and accumulation-mode (A-MOS) structures. When incorporated into the VCO tank circuit, the large-signal swing of the VCO output oscillation modulates the varactor capacitance in time, resulting in a VCO tuning curve that deviates from the dc tuning curve of the particular varactor structure. This paper presents a detailed analysis of this large-signal effect. Simulated results are compared to measurements for an example 2.5-GHz complementary -G/sub m/ LC VCO using I-MOS varactors implemented in 0.35-/spl mu/m CMOS technology.

155 citations


Book ChapterDOI
Behzad Razavi1
01 Jan 2003
TL;DR: In this article, two 1.8 GHz CMOS voltage-controlled oscillators (VCO's), tuned by an inversion-mode MOS varactor and an accumulation-mode VOC, were implemented in a standard O.6-mm CMOS process.
Abstract: This paper presents two 1.8-GHz CMOS voltage-controlled oscillators (VCO's), tuned by an inversion-mode MOS varactor and an accumulation-mode MOS varactor, respectively. Both VCO-s show a lower power consumption and a lower phase noise than a reference VCO tuned by a more commonly used diode varactor. The best overall performance is displayed by the accumulation- mode MOS varactor VCO. The VCO's were implemented in a standard O.6-??m CMOS process.

143 citations


Patent
13 Nov 2003
TL;DR: In this article, a transmission line configured as a looped-stub resonator is disclosed, which can be used as a frequency selective element for an oscillator, such as a VCO of a phase locked loop.
Abstract: A transmission line configured as a looped-stub resonator is disclosed, which can be used as a frequency selective element for an oscillator, such as a VCO of a phase locked loop. The transmission line is a fraction of an electrical wavelength, and can be embedded to provide an inner resonant layer of an overall layered structure. The transmission line is formed into a loop or multiple loops and may be terminated with a capacitor, short circuit, or open circuit. In the embedded case, dielectric insulating material can be used to surround the transmission line on top and bottom surfaces as layers. In addition, electrically conducting material layers can be used to surround the dielectric insulating material.

128 citations


Patent
30 Sep 2003
TL;DR: In this paper, a frequency management scheme for a hybrid cellular/GPS or other device generates a local clock signal for the communications portion of the device, using a crystal oscillator or other part.
Abstract: A frequency management scheme for a hybrid cellular/GPS or other device generates a local clock signal for the communications portion of the device, using a crystal oscillator or other part. The oscillator output may be corrected by way of an automatic frequency control (AFC) circuit or software, to drive the frequency of that clock signal to a higher accuracy. Besides being delivered to the cellular or other communications portion of the hybrid device, the compensated clock signal may also be delivered to a comparator to measure the offset between the cellular oscillator and the GPS oscillator. The error in the cellular oscillator may be measured from the AFC operation in the cellular portion of the device. An undershoot or overshoot in the delta between the two oscillators may thus be deduced to be due to bias in the GPS oscillator, whose value may then be determined. That value may then be used to adjust Doppler search, bandwidth or other GPS receiver characteristics to achieve better time to first fix or other performance characteristics.

125 citations


Journal ArticleDOI
TL;DR: In this paper, a 10 GHz quadrature LC-VCO (QVCO) fabricated in a 0.13/spl mu/m CMOS process for 10-Gb/s multirate optical applications is described.
Abstract: A 10-GHz quadrature LC-VCO (QVCO) fabricated in a 0.13-/spl mu/m CMOS process for 10-Gb/s multirate optical applications is described. Bimodal oscillation behavior (or phase ambiguity) inherent to quadrature LC-VCOs is analyzed theoretically and a cascode-based coupling method is proposed which effectively eliminates bimodal oscillation. Digitally controlled capacitor arrays are used in this design to extend the tuning range of the QVCO to cover multirate operations. The QVCO achieves a jitter generation of only 32 mUI/sub pp/ at 10 GHz and a phase noise of -95 dBc/Hz at 1-MHz frequency offset with only 8 mA of current consumption in the QVCO core.

Proceedings ArticleDOI
09 Feb 2003
TL;DR: In this article, a 1.5GHz CMOS differential VCO was used to reduce the spectral density of up-converted flicker noise by 20dB, reaching the phase noise target of -105dBc/Hz at 50kHz offset required for the PDC receive VCO.
Abstract: A 1.5GHz CMOS differential VCO reduces the spectral density of up-converted flicker noise by 20dB, thereby reaching the phase noise target of -105dBc/Hz at 50kHz offset required for the PDC receive VCO. Flicker noise is suppressed by this amount across almost the entire tuning range from 1.43 to 1.64GHz, while drawing 6mA from a 2.7V supply.

Proceedings ArticleDOI
16 Sep 2003
TL;DR: In this paper, a four-stage CMOS ring oscillator with quadrature outputs and oscillator core current consumption roughly proportional to operating frequency is presented, which is implemented in a 0.18/spl mu/A standard CMOS technology.
Abstract: A 100 MHz to 3.5 GHz four-stage CMOS ring oscillator with quadrature outputs and oscillator core current consumption roughly proportional to operating frequency is presented. A novel oscillator topology consisting of a chain of four static single-ended CMOS inverters, four additional feedforward inverters and frequency control by steering the total oscillator core current is proposed. The circuit is implemented in a 0.18/spl mu/ standard CMOS technology. Oscillator core current consumption is 90/spl mu/A at 100 MHz and 9mA at 3.5 GHz with a 1.8V supply. Measured phase noise at 4 MHz offset is -114dBc/Hz at 100MHz and -106dBc/Hz at 3.5GHz oscillation frequency. Quadrature error is better than 3.5/spl deg/ over the 100 MHz to 3GHz frequency range.

Patent
08 Oct 2003
TL;DR: In this paper, a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) was proposed to synthesize high frequency signals, such as wireless communication signals.
Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may include an analog control loop in which a phase detector circuit and sample and hold circuit are utilized. The output of the sample and hold circuit may be provided to the PLL VCO as VCO input control signals.

Journal ArticleDOI
TL;DR: In this article, a 1-V 3.8 - 5.7 GHz wideband voltage-controlled oscillator (VCO) in a 0.13/spl mu/m silicon-on-insulator (SOI) CMOS process is presented.
Abstract: In this paper, a 1-V 3.8 - 5.7-GHz wide-band voltage-controlled oscillator (VCO) in a 0.13-/spl mu/m silicon-on-insulator (SOI) CMOS process is presented. This VCO features differentially tuned accumulation MOS varactors that: 1) provide 40% frequency tuning when biased between 0 - 1 V and 2) diminish the adverse effect of high varactor sensitivity through rejection of common-mode noise. This paper shows that, for differential LC VCOs, all low-frequency noise such as flicker noise can be considered to be common-mode noise, and differentially tuned varactors can be used to suppress common-mode noise from being upconverted to the carrier frequency. The noise rejection mechanism is explained, and the technological advantages of SOI over bulk CMOS in this regard is discussed. At 1-MHz offset, the measured phase noise is -121.67 dBc/Hz at 3.8 GHz, and -111.67 dBc/Hz at 5.7 GHz. The power dissipation is between 2.3 - 2.7-mW, depending on the center frequency, and the buffered output power is -9 dBm. Due to the noise rejection, the VCO is able to operate at very low voltage and low power. At a supply voltage of 0.75 V, the VCO only dissipates 0.8 mW at 5.5 GHz.

Journal ArticleDOI
TL;DR: In this paper, a new method for deriving an equation for the oscillation frequency of a ring oscillator is proposed, which is general enough to be used for a variety of types of delay stages.
Abstract: A new method for deriving an equation for the oscillation frequency of a ring oscillator is proposed. The method is general enough to be used for a variety of types of delay stages. Furthermore, it provides a framework to include various parasitic and secondary effects. The method is used to derive an equation for a common ring oscillator topology. The validity of the method and the resulting equation have been verified through simulation. The oscillation frequencies predicted by the proposed method are more accurate than existing equations and account for more secondary effects.

Journal ArticleDOI
TL;DR: In this article, a fully integrated quadrature VCO at 8 GHz was implemented using a transformer-based LC tank in 0.18 /spl mu/m CMOS technology, in which two VCOs are coupled to generate I-Q signals.
Abstract: A fully integrated quadrature VCO at 8 GHz is presented. The VCO is implemented using a transformer-based LC tank in 0.18 /spl mu/m CMOS technology, in which two VCOs are coupled to generate I-Q signals. The VCO is realized employing the drain-gate transformer feedback configuration proposed here. This makes use of the quality factor enhancement in the resonator using a transformer and the deep switching-off technique by controlling gate bias. By turning off switching transistors of the differential VCO core deeply, the phase noise performance is improved more than 10 dB. The measured phase noise values are -110 and -117 dBc/HZ at the offset frequencies of 600 kHz and 1 MHz respectively. The tuning range of 250 MHz is achieved with the control voltage from 0 to 1 V. The VCO draws 8 mA in two differential core circuits from 3 V supply. When the bias voltage goes down to 2.5 V, the phase noise decrease only 2 dB compared to that of 3 V bias. The VCO performances are compared with previously reported quadrature Si VCOs in 5/spl sim/12 GHz frequency range.

Book
01 Jan 2003
TL;DR: In this paper, the authors present the phase-switching Dual-Modulus Prescaler (DSP) and Phase-Locked Loop Frequency Synthesizer (SLF) for the DCS-1800 system.
Abstract: I: Abstract. List of Symbols and Abbreviations. Table of Contents. 1: Introduction. 1.1. Telecommunications: An Overview. 1.2. Telecommunications: A Market Perception. 1.3. Integration: Why, How and In What? 1.4. The Research Book. 1.5. The Outline of the Book. 2: On Frequency Synthesis. 2.1. Introduction. 2.2. Indirect or Phase-Locked Loop Frequency Synthesizers. 2.3. The Synthesizer Data Sheet. 2.4. Introduction to PLL building blocks. 2.5. Advanced PLL Frequency Synthesizers. 2.6. Frequency Synthesis for the DCS-1800 System. 2.7. Conclusion. 3: High-Speed CMOS Prescalers. 3.1. Introduction. 3.2. The Phase-Switching Dual-Modulus Prescaler. 3.3. A Single-Ended 1.5 GHz 8/9 Dual-Modulus Prescaler in 0.7 mum CMOS. 3.4. A Single-ended 1.8 GHz 8/9 DMP in 0.8 mum 'Radiation Hardened' BiCMOS. 3.5. A 1.8 GH.z 16-modulus /64-/79 Prescaler in 0.25 mum CMOS. 3.6. A 12 GHz /128 Prescaler in 0.25 mum CMOS. 3.7. Conclusion. 4: Monolithic CMOS LC-VCOs. 4.1. Introduction. 4.2. General Oscillator Theory. 4.3. A Design-Oriented Non-Linear Phase Noise Theory. 4.4. Integrated LC-tanks in CMOS. 4.5. The VCO Circuit Design. 4.6. Implementations. 4.7. Comparison with Published State-of-the-Art VCOs. 4.8. Conclusion. 5: Monolithic Phase Loops. 5.1. Introduction. 5.2. Loop Filter Topology Selection. 5.3. Dual-Path Fourth-Order PLL. 5.4. The PLL Building Block Circuits. 5.5. Experimental Results. 5.6. Conclusion. 6: A 1.8 GHz CMOS DS Fractional-N Frequency Synthesizer. 6.1. Introduction. 6.2. The Fractional-N Principle. 6.3. Conventional Fractional Compensation Methods. 6.4. DS Modulation in Fractional-N Synthesis. 6.5. DS Modulators for Fractional-N Synthesis. 6.6. The Theoretical DS Phase Noise Analysis. 6.7. A Fast Non-Linear DS Phase Noise Analysis Method. 6.8. The Fractional-N Synthesizer Circuit Design. 6.9. Experimental Results. 6.10. Conclusion. 7: Conclusions. 7.1. A 2V CMOS Cellular Transceiver Front-End. 7.2. Main Contributions and Achievements. 7.3. Epilogue. A: DS Modulators with DC-inputs. B: Additional Results of the Non-Linear Analysis for Fractional-N Synthesizers. Index. Bibliography.

Patent
14 Apr 2003
TL;DR: In this article, a frequency synthesizer, a calibrator thereof, and an operating controller thereof are described, which comprises a main charge pump that drives a voltage controlled oscillator (VCO) through a loop filter.
Abstract: A frequency synthesizer, a calibrator thereof, and an operating controller thereof are described. The synthesizer comprises a main charge pump that drives a voltage controlled oscillator (VCO) through a loop filter. The calibrator includes a second, replica charge pump that can also drive the VCO, but is set up to output only its maximum or minimum analog output control voltage. Since the construction and characteristics of the replica charge pump duplicate the main charge pump, the main charge pump's minimum and maximum analog control outputs can be cloned out to the VCO on demand. A VCO calibration procedure therefore includes switching the VCO to each of its ranges set by a bank of fixed capacitors, and using the replica charge pump to drive the VCO to its minimum and maximum frequency for each range setting. The min-max frequency data is stored in a lookup table, and operational requests to switch to a new channel frequency can be supported with a priori information about which fixed-capacitor range selection will be best. The operating point controller includes a sensor to sense the operating point and a controller that provides a switching input to a switchable bank of capacitors to change the operating point. The change can be determined according to calibration data.

Journal ArticleDOI
TL;DR: In this paper, a 1.8 GHz fractional-N frequency synthesizer implemented in 0.6 /spl mu/m CMOS with an on-chip multiphase voltage-controlled oscillator (VCO) exhibits no spurs resulting from phase interpolation.
Abstract: A 1.8 GHz fractional-N frequency synthesizer implemented in 0.6 /spl mu/m CMOS with an on-chip multiphase voltage-controlled oscillator (VCO) exhibits no spurs resulting from phase interpolation. The proposed architecture randomly selects output phases of a multiphase VCO for fractional frequency division to eliminate spurious tones. Measured phase noise at 1.715 GHz is lower than -80 dBc/Hz within a 20 kHz loop bandwidth and -118 dBc/Hz at 1 MHz offset with no fractional spurs above -70 dBc/Hz. The synthesizer has a frequency resolution step smaller than 10 Hz. The chip consumes 52 mW at 3.3 V and occupies 3.7 mm/spl times/2.9 mm.

Journal ArticleDOI
TL;DR: In this paper, a phase-noise analysis of a self-injection-locked GaAs MESFET oscillator operating at the X-band with delay cable loops is presented.
Abstract: Phase-noise analysis of the self-injection-locked oscillator is presented in this paper. The analysis is developed for different oscillator models and arbitrary self-injection feedback loops. The results are illustrated with specific cases of simple time-delay cable and a high-Q factor resonator. It is shown that the behavior of the phase noise is similar to an oscillator locked to an external low phase-noise source. The output phase noise can be reduced at the noise offset frequency near the carrier frequency, and returning to the free-running oscillator noise far from the carrier frequency for certain stable feedback delay ranges. The phase-noise reduction is affected by the self-injection signal strength and feedback transfer function for different oscillator equivalent-circuit models. The theory is verified by using a self-injection-locked GaAs MESFET oscillator operating at the X-band with delay cable loops. The self-injection-locked technique may be used to improve the phase noise of the existing oscillators.

Proceedings ArticleDOI
03 Dec 2003
TL;DR: A CMOS VCO has been designed and fabricated in a commercial 0.25 /spl mu/m CMOS process, using a combination of switched binary-weighted capacitors and standard varactors to achieve a 28% tuning range with a control voltage ranging from 0-2 V, while maintaining a tuning sensitivity over its entire frequency range.
Abstract: A CMOS VCO has been designed and fabricated in a commercial 0.25 /spl mu/m CMOS process. Using a combination of switched binary-weighted capacitors and standard varactors, this VCO achieves a 28% tuning range with a control voltage ranging from 0-2 V, while maintaining a tuning sensitivity of less than 75 MHz/V over its entire frequency range. Compact choke inductors are used in place of resistors to provide a low noise bias point to the varactors. The choke inductors achieve more than 90 nH of effective inductance while consuming a die area of only 92/spl times/92 /spl mu/m/sup 2/. The measured single-sided phase noise is -127 dBc/Hz at a 600 kHz offset from a 1.24 GHz carrier when the VCO core is drawing 3.6 mA from a 2 V supply.

Journal ArticleDOI
TL;DR: In this paper, a 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-/spl mu/m standard CMOS technology, which exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption.
Abstract: A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-/spl mu/m standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 2/sup 31/-1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10/sup -6/ for 2/sup 31/-1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply.

Proceedings ArticleDOI
08 Jun 2003
TL;DR: In this paper, a dual-band radio transceiver chip for 802.11a, 802.,11b, and 802,11g applications is presented in a 0.25 /spl mu/m 40 GHz BiCMOS technology.
Abstract: A fully monolithic dual-band radio transceiver chip for 802.11a, 802.11b and 802.11g applications is presented in a 0.25 /spl mu/m 40 GHz BiCMOS technology. The transceiver chip contains a complete receiver chain with low noise amplifier, mixer, programmable gain amplifier, CCK and OFDM channel filters. In the transmit path, a direct-modulation transmitter with integrated anti aliasing filters and programmable gain control is implemented. The frequency synthesizer consists of a fully integrated VCO, a reference oscillator and a phase locked loop for both supported frequency bands of 2.4 GHz and 5 GHz. For a 3 V power supply, the overall power consumption for 802.11a receive-mode and transmit-mode are 600 mW and 450 mW, respectively.

Journal ArticleDOI
TL;DR: Several practical techniques for specifying the noise and linearity of components used in a /spl Delta//spl Sigma/ fractional-N synthesizer with an in-band phase noise floor are developed.
Abstract: This paper reviews several techniques used to reduce the in-band phase noise contribution of /spl Delta//spl Sigma/ fractional-N frequency synthesizers. The paper develops several practical techniques for specifying the noise and linearity of components used in a /spl Delta//spl Sigma/ fractional-N synthesizer. As an example, it presents a synthesizer with an in-band phase noise floor of -97 dBc/Hz@10 KHz for an RF output frequency of 2.432 GHz and a reference frequency of 16 MHz. The synthesizer has a frequency resolution of 61 Hz and an on-chip crystal oscillator. The synthesizer was implemented in a 0.35-/spl mu/m SiGe process and consumes 6 mA from a 3 V supply. The in-band phase-noise, spurs, and power consumption of this synthesizer are each low and comparable to the state of the art.

Journal ArticleDOI
TL;DR: In this paper, a tunable-feedback ring-resonator oscillator using a voltage-controlled piezoelectric transducer (PET) is introduced, which is constructed by a ring resonator with a pair of orthogonal feed lines as a feedback structure.
Abstract: A tunable-feedback ring-resonator oscillator using a voltage-controlled piezoelectric transducer (PET) is introduced. The new oscillator is constructed by a ring resonator with a pair of orthogonal feed lines as a feedback structure. The ring resonator with two orthogonal feed lines can suppress odd modes and operate at even modes. This operation shows a similar characteristic of high operating oscillation frequencies as that of the push-push oscillators. The high operating resonant frequency characteristic is predicted by a simple transmission-line model. The simulated and measured results agree well with each other. At a fixed frequency of 12.09 GHz, the oscillator has a high DC-to-RF efficiency of 48.7% with an output power of 5.33 dBm. A voltage-controlled PET is used to vary the resonant frequencies of the ring resonator, which, in turn, tunes the oscillator with a good tuning rage of 4.25% around 12 GHz. This tuned oscillator operating at high oscillation frequency can be used in many wireless and sensor systems.

Patent
20 Feb 2003
TL;DR: In this paper, a method and apparatus for compensating an oscillator in a location-enabled wireless device is described, where the frequency error of the oscillator is compensated using the adjusted temperature model.
Abstract: A method and apparatus for compensating an oscillator in a location-enabled wireless device is described. In an example, a mobile device includes a wireless receiver for receiving wireless signals and a GPS receiver for receiving GPS signals. The mobile device also includes an oscillator having an associated temperature model. A frequency error is derived from a wireless signal. The temperature model is adjusted in response to the frequency error and a temperature proximate the oscillator. Frequency error of the oscillator is compensated using the adjusted temperature model. In another example, a frequency error is derived using a second oscillator within the wireless receiver.

Journal ArticleDOI
TL;DR: In this article, both analog and digital automatic-amplitude control techniques for voltage-controlled oscillators (VCOs) are presented to keep the VCOs at an optimum amplitude over temperature, process, and voltage variations.
Abstract: This paper presents both analog and digital automatic-amplitude control techniques for voltage-controlled oscillators (VCOs). These feedback mechanisms help to keep the VCOs at an optimum amplitude over temperature, process, and voltage variations. The VCOs were fabricated in a 50-GHz SiGe BiCMOS process. They use MOS varactors and achieve a 600-MHz tuning range in the 2-GHz band. The phase noise of the VCO with analog control was measured to be -99 dBc/Hz at 100-kHz offset from the carrier. The digital loop allows for a more optimized VCO core that achieves a phase noise of -108.5 dBc/Hz at 100-kHz offset in a low-gain mode. Techniques for suppressing the phase noise in regions of high gain are also presented. The VCOs draw between 4 and 8 mA from a 3.3-V supply.

Patent
Tsung-Hsien Lin1
27 May 2003
TL;DR: An analog open-loop voltage controlled oscillator (VCO) calibration circuit and method for selecting the frequency of the VCO for a phase locked loop (PLL) is presented in this article.
Abstract: An analog open-loop voltage controlled oscillator (VCO) calibration circuit and method for selecting the frequency of the VCO for a phase locked loop (PLL). A frequency divider module produces a 50% duty cycle divided local oscillation and a 50% duty cycle divided reference signal, wherein the divided signals are substantially equal. A period-to-voltage conversion module converts the divided local oscillation signal and the divided reference signal to voltages proportional to the divided signals. A comparator module produces a frequency adjustment signal based on a comparison of the proportional voltages and couples the frequency adjustment signal to a logic module which produces a frequency compensation signal based on the frequency adjustment signal. The frequency compensation signal functions to adjust the configuration of switched capacitors in a capacitor bank, coupled to the VCO tuned circuit, until the divided local oscillation signal is substantially equal to the divided reference signal.

Proceedings ArticleDOI
09 Feb 2003
TL;DR: In this paper, a single-chip Bluetooth transceiver in 018/spl mu/m CMOS integrates a direct VCO modulation transmitter and 15MHz-IF receiver to reduce power consumption and cost.
Abstract: A single-chip Bluetooth transceiver in 018/spl mu/m CMOS integrates a direct VCO modulation transmitter and 15MHz-IF receiver to reduce power consumption and cost The receiver achieves a sensitivity of -77dBm and transmitting power of +4dBm