Showing papers on "Voltage-controlled oscillator published in 2004"

A study of injection locking and pulling in oscillators

Abstract: Injection locking characteristics of oscillators are derived and a graphical analysis is presented that describes injection pulling in time and frequency domains. An identity obtained from phase and envelope equations is used to express the requisite oscillator nonlinearity and interpret phase noise reduction. The behavior of phase-locked oscillators under injection pulling is also formulated.

A fully integrated 24-GHz eight-element phased-array receiver in silicon

Abstract: This paper reports the first fully integrated 24-GHz eight-element phased-array receiver in a SiGe BiCMOS technology. The receiver utilizes a heterodyne topology and the signal combining is performed at an IF of 4.8 GHz. The phase-shifting with 4 bits of resolution is realized at the LO port of the first down-conversion mixer. A ring LC voltage-controlled oscillator (VCO) generates 16 different phases of the LO. An integrated 19.2-GHz frequency synthesizer locks the VCO frequency to a 75-MHz external reference. Each signal path achieves a gain of 43 dB, a noise figure of 7.4 dB, and an IIP3 of -11 dBm. The eight-path array achieves an array gain of 61 dB and a peak-to-null ratio of 20 dB and improves the signal-to-noise ratio at the output by 9 dB.

On the phase-noise and phase-error performances of multiphase LC CMOS VCOs

Abstract: This paper presents an analysis of phase noise in multiphase LC oscillators, and measurement results for several CMOS quadrature-voltage-controlled-oscillators (QVCOs) working in the 2-GHz frequency range. The phase noise data for a so-called BS-QVCO (-140 dBc/Hz or less at 3 MHz frequency offset from the carrier, for a power consumption of 20.8 mW and a figure-of-merit of 184 dBc/Hz) show that phase noise performances are close to the previously derived limits. A systematic cause of departure from ideal quadrature between QVCO signals is also analyzed and measured experimentally, and a compact LC-tank layout that removes this source of phase error is proposed. A TS-QVCO designed with this technique shows a phase-noise figure-of-merit improvement of 4 dB, compared to a previous implementation. The measured equivalent phase error for all QVCOs is between 0.6/spl deg/ and 1/spl deg/.

Analysis and design of injection-locked LC dividers for quadrature generation

Abstract: Injection-locked LC dividers for low-power quadrature generation are discussed in this paper Modeling the circuits as regenerative frequency dividers leads to very simple analytical expressions for the locking band, phase deviation from quadrature and phase noise Maximizing the ratio between the injected and the biasing current is beneficial to all the above parameters whereas reducing the tank quality factor improves locking band and quadrature accuracy, though at the expense of current consumption, for given output amplitude To validate the theory, experiments have been carried on a 018-/spl mu/m CMOS direct conversion IC, embedding an injection-locked quadrature generator, realized for the Universal Mobile Telecommunication System Frequency locking range as large as 24% and phase deviation from quadrature around 08/spl deg/ are measured while each divider consumes 2 mA The phase noise of the quadrature generator is determined by the driving oscillator phase noise because the dividers contribution is easily made negligible up to hundreds of megahertz offset

A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications

Abstract: A /spl Sigma//spl Delta/ fractional-N frequency synthesizer targeting WCDMA receiver specifications is presented. Through spurs compensation and linearization techniques, the PLL bandwidth is significantly extended with only a slight increase in the integrated phase noise. In a 0.18-/spl mu/m standard digital CMOS technology a fully integrated prototype with 2.1-GHz output frequency and 35 Hz resolution has an area of 3.4 mm/sup 2/ PADs included, and it consumes 28 mW. With a 3-dB closed-loop bandwidth of 700 kHz, the settling time is only 7 /spl mu/s. The integrated phase noise plus spurs is -45 dBc for the first WCDMA channel (1 kHz to 1.94 MHz) and -65 dBc for the second channel (2.5 to 6.34 MHz) with a worst case in-band (unfiltered) fractional spur of -60 dBc. Given the extremely large bandwidth, the synthesizer could be used also for TX direct modulation over a broad band. The choice of such a large bandwidth, however, still limits the spur performance. A slightly smaller bandwidth would fulfill WCDMA requirements. This has been shown in a second prototype, using the same architecture but employing an external loop filter and VCO for greater flexibility and ease of testing.

Fully integrated SiGe VCOs with powerful output buffer for 77-GHz automotive Radar systems and applications around 100 GHz

Abstract: It is demonstrated that SiGe bipolar technologies are well suited for voltage-controlled oscillators (VCOs) in 77-GHz automotive radar systems. For this, the design of a VCO with powerful output buffer (with good decoupling capability and high output power), comparatively wide tuning range, and reasonably low phase noise is described. To achieve the required high output power, the potential operating range of the output transistors, limited by high-current effects and avalanche breakdown, respectively, had to be exploited using adequate transistor models. The VCOs need a single supply voltage only and have been fully integrated (including resonant circuit and output buffer) on a single small (1 mm/sup 2/) chip, demonstrating their low-cost potential. Experimental results showed, at a center frequency of around 77 GHz, a usable tuning range of 6.7 GHz and a phase noise of -97 dBc/Hz at 1-MHz offset frequency averaged over this range. In addition, the center oscillation frequency can be coarsely adjusted within a wide range by cutting links in the upper metallization layer. The total signal power delivered by both buffer outputs together is as high as 18.5 dBm at a power consumption of 1.2 W. Simulations let us expect a potential doubling of the output power (for two or four outputs) by extension of the output buffer. To get an impression of the maximum frequency achievable with the circuit concept and technology used, a second VCO (again with buffered output) has been developed. To the best of the authors' knowledge, the measured maximum oscillation frequency of about 100 GHz, at 12.4-dBm total output power (14.3 dBm at 99 GHz), is a record value for SiGe VCOs with buffered output operating at their fundamental frequency. The usable tuning range is still 6.2 GHz.

Analysis of the PLL jitter due to power/ground and substrate noise

Abstract: Phase-locked loops (PLL) in radio-frequency (RF) and mixed analog-digital integrated circuits (ICs) experience substrate coupling due to the simultaneous circuit switching and power/ground (P/G) noise which translate to a timing jitter. In this paper. an analysis of the PLL timing jitter due to substrate noise resulting from P/G noise and large-signal switching is presented. A general comprehensive stochastic model of the substrate and P/G noise sources in very large-scale integration (VLSI) circuits is proposed. This is followed by calculation of the phase noise of the constituent voltage-controlled oscillator (VCO) in terms of the statistical properties of substrate and P/G noise. The PLL timing jitter is then predicted in response to the VCO phase noise. Our mathematical method is utilized to study the jitter-induced P/G noise in a CMOS PLL, which is designed and simulated in a 0.25-/spl mu/m standard CMOS process. A comparison between the results obtained by our mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.

A very low-power quadrature VCO with back-gate coupling

Abstract: A new quadrature voltage-controlled oscillator (QVCO) topology is proposed where the back-gates of the core transistors are used as coupling terminals. The use of back-gates reduces the power dissipation and removes the additional noise contributions compare to the conventional coupling transistor based topology. The advantages of the proposed QVCO topology in comparison with prior works are exploited based on simulation. A QVCO based on the proposed topology with additional design ideas has been implemented using a 0.18-/spl mu/m triple-well technology for 1 GHz-band operation, and measurement shows the phase noise of -120 dBc/Hz at 1-MHz offset with output power of 2.5 dBm, while dissipating only 3 mA for the whole QVCO from 1.8-V supply.

Dc-dc converter with reduced electromagnetic interference

Abstract: A DC-DC converter includes a variable frequency oscillator (36), a control system and a power train. The DC-DC converter is well suited for use in a cell phone. The control system uses the output of the oscillator to control the power train. The oscillator varies its frequency as a function of a pseudo random number generator (60), thereby reducing electromagnetic interference caused by ripple in the output of the DC-DC converter.

60GHz transceiver circuits in SiGe bipolar technology

Abstract: A 60GHz LNA, direct-downconverter, PA, and 20GHz VCO are built in a 200GHz f/sub t/,/f/sub max/, 0.12/spl mu/m SiGe technology. The 10.8mW LNA has 15dB gain, 3.4-4.4dB noise figure and -8.5dBm IIP3. The down converter has 16dB gain, >50dB LO-RF isolation, and 13.4-14.8dB noise figure. The PA delivers 10dBm at 9dB gain.

Capturing oscillator injection locking via nonlinear phase-domain macromodels

Abstract: Injection locking is a nonlinear dynamical phenomenon that is often exploited in electronic and optical oscillator design. Behavioral modeling techniques for oscillators that predict this phenomenon accurately are of significant scientific and practical importance. In this paper, we propose a nonlinear approach for generating small phase-domain oscillator/voltage-controlled oscillator (VCO) macromodels that capture injection locking well. Our nonlinear phase-domain macromodels are closely related to recent oscillator phase noise and jitter theories, and can be extracted efficiently by algorithm from SPICE-level descriptions of any oscillator or VCO. Using LC and ring oscillators as test cases, we confirm the ability of nonlinear phase macromodels to capture injection locking, and also obtain significant computational speedups over full SPICE-level circuit simulation. Furthermore, we show that our approach is equally effective for capturing the dynamics of transition to locking, including unlocked tones and phase jump phenomena.

A /spl Sigma/-/spl Delta/ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications

Abstract: A fractional-N frequency synthesizer (FNFS) in a 0.5-/spl mu/m SiGe BiCMOS technology is implemented. In order to operate in a wide-band frequency range, a switched-capacitors bank LC tank voltage-controlled oscillator (VCO) and an adaptive frequency calibration (AFC) technique are used. The measured VCO tuning range is as wide as 600 MHz (40%) from 1.15 to 1.75 GHz with a tuning sensitivity from 5.2 to 17.5 MHz/V. A 3-bit fourth-order /spl Sigma/-/spl Delta/ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3 Hz as well as agile switching time. The experimental results show -80 dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and -129 dBc/Hz out-of-band phase noise at 400-kHz offset frequency. The fractional spurious is less than -70 dBc/Hz at 300-kHz offset frequency and the reference spur is -75 dBc/Hz. The lock time is less than 150 /spl mu/s. The proposed synthesizer consumes 19.5 mA from a single 2.8-V supply voltage and meets the requirements of GSM/GPRS/WCDMA applications.

Low-power 5 GHz LNA and VCO in 90 nm RF CMOS

Abstract: The potential of 90 nm CMOS technology for low-power RF front-ends is demonstrated with fully integrated low-voltage Low-Noise Amplifiers (LNA) and Voltage-Controlled Oscillators (VCO). The 5.5 GHz LNA draws 3.5 mA from a 0.6 V supply with a measured power gain of 11.2 dB, and a 3.2 dB noise figure. The 6.3 GHz VCO has a phase noise of -118 dBc/Hz at 1 MHz offset, drawing 4.9 mA from a 1.2 V supply.

64 GHz and 100 GHz VCOs in 90 nm CMOS using optimum pumping method

Abstract: A method to optimally pump energy from the transistors to the passive network is presented for the design of integrated 64 GHz and 100 GHz VCOs in 90 nm CMOS. The VCOs use an on-die distributed network, draw /spl sim/25 mA from a 1 V supply and produce oscillations with 0.4 Vp-p amplitudes. Phase noise is <-110 dBc/Hz at 10 MHz offset, and VCO gain is 2 GHz/V.

Development of 60-GHz front-end circuits for a high-data-rate communication system

Abstract: Recent results from a Swedish program for development of 60-GHz monolithic microwave integrated circuits (MMICs) for high-data-rate communication links are presented. Front-end circuits such as mixers, amplifiers, frequency multipliers, IF amplifiers with gain control, and voltage-controlled oscillators (VCOs) have been realized utilizing GaAs PHEMT and MHEMT technologies. A newly developed 7.5-GHz coupled Colpitt VCO shows a minimum phase noise of -95 dBc at 100 kHz offset. A second-harmonic 14-GHz VCO shows a minimum phase noise of less than -90 dBc at 100 kHz. A novel balanced 7-28-GHz MMIC frequency quadrupler is described and compared with a single-ended quadrupler at the same input frequencies. To demonstrate its feasibility and potential application, the quadrupler is combined with the Colpitt VCO and the output characteristics of the resulting 30-GHz MMIC source are measured. A three-stage MHEMT wide-band amplifier covering 43-64 GHz with a gain of 24 dB, a minimum noise figure of 2.5 dB, and a passband ripple of 2 dB is also described. In future 60-GHz systems for mass markets where cost is of utmost importance, Si-based technologies, especially CMOS, are highly interesting. Some recent circuit results based on a 90-nm CMOS technology are also reported.

60 GHz VCO with wideband tuning range fabricated on VLSI SOI CMOS technology

Abstract: A 60 GHz cross-coupled differential LC CMOS VCO is presented in this paper, which is optimized for a large frequency tuning range using conventional MOSFET varactors. The MMIC is fabricated on digital 90 nm SOI technology and requires a circuit area of less than 0.1 mm/sup 2/ including the 50 /spl Omega/ output buffers. Within a frequency control range from 52.3 GHz to 60.6 GHz, a supply voltage of 1.5 V and a supply current of 15 mA, the circuit dividers a very constant output power of -6.8 /spl plusmn/ 0.2 dBm and yields a phase noise between -85 to -92 dBc/Hz at 1 MHz frequency offset.

Integrated low noise microwave wideband push-push vco

Abstract: In one aspect, a voltage controlled oscillator is provided that includes circuitry comprising tunable coupled resonator networks, which are coupled to a terminal of a pair of three-terminal devices through a tuning voltage network which supports wide-band tunability. In another aspect, a wide-band tunable resonator is provided that is amenable to integration in the integrated circuit form.

A fully integrated 24-GHz eight-element phased-array receiver in silicon

Abstract: This paper reports the first fully integrated 24-GHz eight-element phased-array receiver in a SiGe BiCMOS technology. The receiver utilizes a heterodyne topology and the signal combining is performed at an IF of 4.8 GHz. The phase-shifting with 4 bits of resolution is realized at the LO port of the first down-conversion mixer. A ring LC voltage-controlled oscillator (VCO) generates 16 different phases of the LO. An integrated 19.2-GHz frequency synthesizer locks the VCO frequency to a 75-MHz external reference. Each signal path achieves a gain of 43 dB, a noise figure of 7.4 dB, and an IIP3 of -11 dBm. The eight-path array achieves an array gain of 61 dB and a peak-to-null ratio of 20 dB and improves the signal-to-noise ratio at the output by 9 dB.

A 5 GHz fully integrated full PMOS low phase noise LC VCO

Abstract: A 5-GHz fully integrated, full PMOS, low-phase-noise and low-power differential voltage-controlled oscillator (VCO) is presented. This circuit is implemented in a 0.35-/spl mu/m four-metal BiCMOS SiGe process. At 2.7-V power supply voltage and a total power dissipation of only 13.5 mW, the proposed VCO features a worst case phase noise of -97 dBc/Hz and -117 dBc/Hz at 100 kHz and 1 MHz frequency offset, respectively. The oscillator is tuned from 5.13 to 5.68 GHz with a tuning voltage varying from 0 to 2.7 V.

Damping characteristics of a fractional oscillator

Abstract: A study of sinusoidally forced oscillations of a fractional oscillator shows that the system exhibits a rich variety of damping characteristics. While some aspects of the damping mimic the characteristic features of a damped harmonic oscillator, there are others, which do not find any parallel in the damped harmonic oscillator system. It is clearly demonstrated that the “free” and “forced” oscillations of a fractional oscillator are characterized by different damping parameters. While both depend on the fractional index α , the “free” oscillation damping depends on the “natural frequency”, ω 0 , of the oscillator, the “forced” oscillation damping depends in addition, on the “driving frequency”, ω . Furthermore, there is a different power-law tail associated with each of these cases.

A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture

Abstract: A 2.4-GHz frequency synthesizer was designed that uses a fractional divider to drive a dual-phase-locked-loop (PLL) structure, with both PLLs using only on-chip ring oscillators. The first-stage narrow-band PLL acts as a spur filter while the second-stage wide-band PLL suppresses VCO phase noise so that simultaneous suppression of phase noise and spur is achieved. A new low-power, low-noise, low-frequency ring oscillator is designed for this narrow-band PLL. The chip was designed in 0.35-/spl mu/m CMOS technology and achieves a phase noise of -97 dBc/Hz at 1-MHz offset and spurs of -55 dBc. The chip's output frequency varies from 2.4 to 2.5 GHz; the chip consumes 15 mA from a 3.3-V supply and occupies 3.7 mm/spl deg/.

Temperature compensated voltage controlled oscillator

Abstract: A VCO with temperature compensation is achieved using reverse biased diodes. The VCO includes an amplifier that provides the required signal gain, a resonator tank circuit that provides the required phase shift, and at least one frequency tuning circuit for tuning the frequency of the oscillator signal. Each frequency tuning circuit includes at least one tuning capacitor and at least one MOS pass transistor that connects or disconnects the tuning capacitor(s) to/from the resonator tank circuit. Each reverse biased diode may be a parasitic diode that is formed at a drain or source junction of a MOS transistor. The reverse biased diodes have capacitance that can be controlled by a reverse bias voltage to compensate for drift in the VCO oscillation frequency over temperature.

/spl Sigma/High-frequency LC VCO design using capacitive degeneration

Abstract: In this paper, we evaluate the high-frequency performance limitations of traditional LC voltage-controlled oscillators (VCOs) that use a cross-coupled negative resistance cell and propose a new topology that overcomes these limitations. The proposed cell is based on a capacitively emitter degenerated topology which uses a cross-coupled MOS pair as the degeneration cell. The cross-coupled MOS pair contributes additional conductance and results in a higher maximum attainable oscillation frequency and better negative resistance characteristics as compared to the other topologies at high frequencies. These properties combined with its small effective capacitance enable low-power low-noise high-frequency VCO implementations. The proposed topology is demonstrated through a 20-GHz fully integrated LC VCO implemented in the IBM SiGe 0.25-/spl mu/m BiCMOS process. A comparison of its figure of merit with previously reported 20-GHz VCOs shows the effectiveness of the proposed topology.

A readout circuit for an intra-ocular pressure sensor

Abstract: A readout circuit for a passive telemetric intra-ocular pressure (IOP) sensor is being developed. The intra-ocular sensor consists of a capacitive pressure sensor in parallel with a planar coil. This inductor–capacitor (LC) resonant circuit transduces the pressure into a shift of resonance frequency. A voltage controlled oscillator (VCO) is used to excite the sensor over a large frequency range (20–40 MHz), hereby detecting resonance of the internal sensor, and thus enabling the measurement of the intra-ocular pressure. This low power circuit is extremely compact, making it suitable for long-term ambulant patient monitoring. The circuit allows wireless readout of the smallest pressure transducers. Tests show promising results at mutual coil distances up to 7.5 mm.

A CMOS self-regulating VCO with low supply sensitivity

Abstract: This paper presents a self-regulating voltage-controlled oscillator (VCO) with low supply sensitivity. With an adaptive delay cell, the self-regulating VCO achieves a low supply sensitivity of 0.15%-delay/1%-supply or less. This delay cell has a built-in compensation circuit that senses and corrects the delay variation caused by supply fluctuation. The proposed scheme rejects device noise as well and hence achieves a low phase noise of -101.4 dBc/Hz at 600-kHz offset when it runs at 900 MHz. The prototype phase-locked loop with the VCO fabricated in 0.35-/spl mu/m CMOS process shows a cycle-to-cycle rms jitter of 2.1 ps at 450 MHz (VCO at 900 MHz) under quiet supply condition.

Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture

Abstract: This paper describes the modeling, design, and characterization of a low-jitter 2.4-GHz LC-VCO PLL architecture realized in a standard 0.12-/spl mu/m CMOS technology. It features an analog dual control loop for fine and coarse VCO tuning that allows very low VCO gain (60 MHz/V) for noise rejection while maintaining a wide tuning range. The coarse input of the VCO is driven by an analog circuit that adjusts the VCO gain in a continuous manner. Measurements demonstrate an integrated jitter of 0.74 ps that is 43% lower compared to results from a standard PLL topology (STD PLL) with a single control loop. The PLLs have the same bandwidth and output frequency range and were built on the same wafer for comparison. The circuit area of the proposed LC-VCO PLL is 0.7 mm/sup 2/ and the power consumption is 32 mW. The area and power consumption of the proposed LC-VCO PLL are less than 1% larger compared to the STD PLL.

Distributed MOS varactor biasing for VCO gain equalization in 0.13 /spl mu/m CMOS technology

Abstract: The paper describes work done on a LC-VCO to linearize its frequency-voltage (Kvco) characteristic in order to extend its versatility. The technology used is a standard 0.13 /spl mu/m CMOS supplied by 1.2 V. The optimization is made on the varactor stage of the resonator and gives a nearly constant Kvco (140/spl plusmn/10 MHz/V from 2.36 GHz to 2.44 GHz), in spite of the MOS varactor non-linear characteristic, with still a good pushing (9 MHz/V) and constant phase noise (-126 dBc/Hz at 3 MHz offset).

Coupled-inductor multi-band VCO

Abstract: A multi-band VCO employs a coupled-inductor based resonator having N≧2 ports. Each port has an inductor and at least one capacitor. The N inductors for the N ports are magnetically coupled. The inductors/ports may be selectively enabled and disabled to allow the VCO to operate at different frequency bands. The capacitor(s) for each port may include one or more fixed capacitors, one or more variable capacitors (varactors), one or more switchable capacitors, or any combination of fixed, variable, and switchable capacitors. The switchable capacitors (if any) in the enabled ports may be selectively enabled and disabled to vary the VCO oscillation frequency. The varactors (if any) in the enabled ports can vary the oscillation frequency to lock the VCO to a desired frequency. The multi-band VCO may be implemented with various oscillator topologies and can replace multiple single-band VCOs.

Voltage controlled oscillator having improved phase noise

Abstract: A frequency agile voltage controlled oscillator is provided in which amplitude control is performed by digitally controlling the current supplied to the oscillator from a current source (10). The use of digital control means that phase noise performance of the oscillator is not degraded by the introduction of noise from the current source controller.

A 21.5/43-GHz dual-frequency balanced Colpitts VCO in SiGe technology

Abstract: A balanced Colpitts voltage-controlled oscillator (VCO) is designed and fabricated in a commercially available 0.25-/spl mu/m SiGe BiCMOS process. It has the characteristics of the push-push VCO, i.e., the VCO has simultaneously a differential output at a fundamental frequency of 21.5 GHz and a single-ended output at the second harmonic frequency of 43 GHz. A differential tuning technique is applied to reduce the phase noise. The measured phase noise at 1-MHz offset is -113 dBc/Hz at 21.5 GHz and -107 dBc/Hz at 43 GHz. The corresponding output power is about -6 and -17 dBm, respectively, with a 5% tuning range and a 130-mW dc power consumption.