Showing papers on "Voltage-controlled oscillator published in 2008"

Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise

Abstract: A harmonic oscillator topology displaying an improved phase noise performance is introduced in this paper. Exploiting the advantages yielded by operating the core transistors in class-C, a theoretical 3.9 dB phase noise improvement compared to the standard differential-pair LC-tank oscillator is achieved for the same current consumption. Further benefits derive from the natural rejection of the tail bias current noise, and from the absence of parasitic nodes sensitive to stray capacitances. Closed-form phase-noise equations obtained from a rigorous time-variant circuit analysis are presented, as well as a time-variant study of the stability of the oscillation amplitude, resulting in simple guidelines for a reliable design. Furthermore, the analysis of phase noise is extended to encompass a general harmonic oscillator, showing that all phase noise relations previously obtained for specific LC oscillator topologies are special cases of a very general and remarkably simple result.

Phase Noise and Frequency Stability in Oscillators

Abstract: Foreword Lute Maleki Foreword David B. Leeson Preface List of symbols 1. Phase noise and frequency stability 2. Phase noise in semiconductors and amplifiers 3. Heuristic approach to the Leeson effect 4. Phase noise and linear feedback theory 5. Noise in delay-line oscillators and lasers 6. Oscillator hacking A Laplace transform Bibliography.

A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer

Abstract: The use of VCO-based quantization within continuous-time (CT) SigmaDelta analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 mum CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth while consuming 40 mW from a 1.2 V supply and occupying an active area of 640 mum times 660 mum. A key element of the ADC structure is a 5-bit VCO-based quantizer clocked at 950 MHz which achieves first-order noise shaping of its quantization noise. The quantizer structure allows the second-order CT SigmaDelta ADC topology to achieve third-order noise shaping, and direct connection of the VCO-based quantizer to the internal DACs of the ADC provides intrinsic dynamic element matching of the DAC elements.

Resonant Tunneling Diodes for Sub-Terahertz and Terahertz Oscillators

Abstract: Resonant tunneling diodes (RTDs) have the potential for use as compact and coherent terahertz (THz) sources operating at room temperature. In this paper, sub-THz and THz oscillators with RTDs integrated on planar circuits are described. Fundamental oscillation up to 0.65 THz and harmonic oscillation up to 1.02 THz were obtained at room temperature in our recent study. Limiting factors for oscillation frequency and output power are theoretically analyzed including tunneling and transit-time effects and parasitic elements. Oscillation frequency and its dependence on RTD size are in good agreement with the measured results. Based on this result, it is shown that fundamental oscillation up to 2.3 THz and an output power of 60 µW at 1 THz are theoretically expected by improving the structures of the RTD and the antenna. Voltage-controlled oscillation, which is useful for the precise control of frequency, is observed in the RTD oscillators. Coherent power combining in an array configuration to achieve high output power as well as mutual injection locking between the array elements are also described.

Grid cells and theta as oscillatory interference: Theory and predictions

Abstract: The oscillatory interference model [Burgess et al. (2007) Hippocampus 17:801-802] of grid cell firing is reviewed as an algorithmic level description of path integration and as an implementation level description of grid cells and their inputs. New analyses concern the relationships between the variables in the model and the theta rhythm, running speed, and the intrinsic firing frequencies of grid cells. New simulations concern the implementation of velocity-controlled oscillators (VCOs) with different preferred directions in different neurons. To summarize the model, the distance traveled along a specific direction is encoded by the phase of a VCO relative to a baseline frequency. Each VCO is an intrinsic membrane potential oscillation whose frequency increases from baseline as a result of depolarization by synaptic input from speed modulated head-direction cells. Grid cell firing is driven by the VCOs whose preferred directions match the current direction of motion. VCOs are phase-reset by location-specific input from place cells to prevent accumulation of error. The baseline frequency is identified with the local average of VCO frequencies, while EEG theta frequency is identified with the global average VCO frequency and comprises two components: the frequency at zero speed and a linear response to running speed. Quantitative predictions are given for the inter-relationships between a grid cell's intrinsic firing frequency and grid scale, the two components of theta frequency, and the running speed of the animal. Qualitative predictions are given for the properties of the VCOs, and the relationship between environmental novelty, the two components of theta, grid scale and place cell remapping. (C) 2008 Wiley-Liss, Inc.

A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer

Abstract: The use of VCO-based quantization within continuous-time (CT) ΣΔ analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 μm CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth while consuming 40 mW from a 1.2 V supply and occupying an active area of 640 μm × 660 μm. A key element of the ADC structure is a 5-bit VCO-based quantizer clocked at 950 MHz which achieves first-order noise shaping of its quantization noise. The quantizer structure allows the second-order CT SA ADC topology to achieve third-order noise shaping, and direct connection of the VCO-based quantizer to the internal DACs of the ADC provides intrinsic dynamic element matching of the DAC elements.

Terahertz CMOS Frequency Generator Using Linear Superposition Technique

Abstract: A low Terahertz (324 GHz) frequency generator is realized in 90 nm CMOS by linearly superimposing quadruple (N=4) phase shifted fundamental signals at one fourth of the output frequency (81 GHz). The developed technique minimizes the fundamental, second and third order harmonics without extra filtering and results in a high fundamental-to-4 th harmonic signal conversion ratio of 0.17 or -15.4 dB. The demonstrated prototype produces a calibrated -46 dBm output power when biased at 1 V and 12 mA with 4 GHz tuning range and extrapolated phase noise of -91 dBc/Hz at 10 MHz frequency offset. The linear superposition (LS) technique can be generalized for all even number cases (N=2k, where k=1,2,3,4,...,n) with different tradeoffs in output power and frequency. As CMOS continues to scale, we anticipate the LS N=4 VCO to generate signals beyond 2 Terahertz by using 22 nm CMOS and produce output power up to -1.5 dBm with 1.7% power added efficiency with an LS VCO + Class-B Power Amplifier cascaded circuit architecture.

Design of Wide Tuning-Range CMOS VCOs Using Switched Coupled-Inductors

Abstract: Two designs of voltage-controlled oscillators (VCOs) with mutually coupled and switched inductors are presented in this paper to demonstrate that the tuning range of an LC VCO can be improved with only a small increase in phase noise and die area in a standard digital CMOS process. Particular attention is given to the layout of the inductors to maintain Q across the tuning range. In addition, different capacitive coarse-tuning methods are compared based on simulated and measured data obtained from test structures. Implemented in a 90 nm digital CMOS process, a VCO with two extra coupled inductors achieves a 61.9% tuning range with an 11.75 GHz center frequency while dissipating 7.7 mW from a 1.2 V supply. This VCO has a measured phase noise of -106 dBc/Hz at 1 MHz offset from the center frequency resulting in a higher figure-of-merit than other recently published VCOs with similar operating frequencies. In addition, the area overhead is only 30% compared to a conventional LC VCO with a single inductor.

Direct Antenna Modulation (DAM) for On-Chip mm-Wave Transceivers

Abstract: In the last few decades the puissant desire to miniaturize the digital circuits to achieve higher speed and larger density has shaped the evolution of the silicon-based technologies. This development opens a new era in the field of millimeter-wave electronics in which many low-cost high-yield silicon-based transistors can be used on a single chip to enable creation of novel architectures with unique properties not achievable with old processes. In addition to this high level of integration capability, the die size of comparable or even larger than the wave-length makes it possible to integrate antennas, transceivers, and digital circuitry all on a single silicon die. It is important to realize that although smaller parasitic capacitors and shorter transistor channels have improved fT and fmax of transistors, extremely thin metal layers, highly doped substrates, and low breakdown voltage transistors have severely affected the performance of analog and RF building blocks. For example, thin metal layers have increased the loss and lowered the quality factor of the building blocks such as capacitors and inductors and low breakdown voltage transistors have made the power generation quite challenging. Additionally, if not carefully designed, small wave-lengths in the millimeter-wave range may cause unintended radiation by on-chip components. In this dissertation, we address these issues in design of millimeter-wave silicon-based single-chip phased-array transceivers with integrated antennas. We also introduce the technique of Direct Antenna Modulation (DAM) and implement two proof-of-concept chips operating at 60 GHz. We will present the receiver and the on-chip antenna sections of a fully integrated 77 GHz four-element phased-array transceiver with on-chip antennas in silicon. The receiver section of the chip includes the complete down-conversion path comprising low-noise amplifier (LNA), frequency synthesizer, phase rotators, combining amplifiers, and on-chip dipole antennas. The signal combining is performed using a novel distributed active combining amplifier at an IF of 26 GHz. In the LO path, the output of the 52 GHz VCO is routed to different elements and can be phase shifted locally by the phase rotators. A silicon lens on the backside is used to reduce the loss due to the surface-wave power of the silicon substrate. Our measurements show a single-element LNA gain of 23 dB and a noise figure of 6.0 dB. Each of the four receive paths has a gain of 37 dB and a noise figure of 8.0 dB. Each on-chip antenna has a gain of +8 dBi. A direct antenna modulation (DAM) technique is also introduced, where the radiated far-field signal is modulated by time-varying changes in the antenna near-field electromagnetic (EM) boundary conditions. This enables the transmitter to send data in a direction-dependent fashion producing a secure communication link. The transmitter architecture makes it possible to use narrow-band highly-efficient switching power amplifiers to transmit wideband constant and non-constant envelope modulated signals. Theoretically, these systems are capable of transmitting independent data in multiple directions at full-rate concurrently using a single transmitter. Direct antenna modulation (DAM) can be performed by using either switches or varactors. Two proof-of-concept DAM transmitters operating at 60GHz using switches and varactors are demonstrated in silicon proving the feasibility of this approach.

Phase noise of a high performance OEO and an ultra low noise floor cross-correlation microwave photonic homodyne system

Abstract: This paper describes two recent types of opto-electronic oscillators. The first is a long fiber opto-electronic oscillator, utilizing a high power laser with long delay, and consisting of low noise components. This oscillator generates a stable 10 GHz signal with phase noise of -163 dBc/Hz at 6 kHz offset from the carrier. The second is a low noise 10 GHz compact opto-electronic oscillator. This latter oscillator consists of coupled optical and microwave loops utilizing a short fiber. We also report on an automatic ultra-low noise floor measurement system, designed and built to measure the phase noise of the above (and other) oscillators. This delay line cross-correlation measurement system utilizes microwave-photonic links, eliminating the need for a second oscillator. This system provides quick and reliable measurement of the oscillator under test.

Switching voltage regulator employing dynamic voltage scaling with hysteretic comparator

Abstract: A switching voltage regulator is disclosed operable to regulate a voltage supplied to system circuitry. A comparator compares an oscillator signal generated by a ring oscillator to a reference signal generated by a frequency generator. Switching circuitry charges a charging element in response to the comparison, and control circuitry adjusts a number of delay elements in the ring oscillator and a divider value of the frequency generator to generate hysteresis in the comparison. In one embodiment, the charging element is charged while a frequency of the reference signal is above a frequency of the oscillator signal.

A Low-Voltage SiGe BiCMOS 77-GHz Automotive Radar Chipset

Abstract: This paper presents a complete 2.5-V 77-GHz chipset for Doppler radar and imaging applications fabricated in SiGe HBT and SiGe BiCMOS technologies. The chipset includes a 123-mW single-chip receiver with 24-dB gain and an IP1 dB of -21.7 dBm at 76-GHz local oscillator (LO) and 77-GHz RF, 4.8-dB double-sideband noise figure at 76-GHz LO and 1-GHz IF, and worst case -98.5 dBc/Hz phase noise at 1-MHz offset over the entire voltage-controlled oscillator tuning range at room temperature. Monolithic spiral inductors and transformers result in a receiver core area of 450 mum times 280 mum. For integration of an entire 77-GHz transceiver, a power amplifier with 19-dB gain, +14.5-dBm saturated output power, and 15.7% power-added efficiency is demonstrated. Frequency divider topologies for 2.5-V operation are investigated and measurement results show a 105-GHz static frequency divider consuming 75 mW, and a 107-GHz Miller divider consuming 33 mW. Measurements on all circuits confirm operation up to 100 deg C. Low-power low-noise design techniques for each circuit block are discussed.

165-GHz Transceiver in SiGe Technology

Abstract: Two D-band transceivers, with and without amplifiers and static frequency divider, transmitting simultaneously in the 80-GHz and 160-GHz bands, are fabricated in SiGe HBT technology. The transceivers feature an 80-GHz quadrature Colpitts oscillator with differential outputs at 160 GHz, a double-balanced Gilbert-cell mixer, 170-GHz amplifiers and broadband 70-GHz to 180-GHz vertically stacked transformers for single-ended to differential conversion. For the transceiver with amplifiers and static frequency divider, which marks the highest level of integration above 100 GHz in silicon, the peak differential down-conversion gain is -3 dB for RF inputs at 165 GHz. The single-ended, 165-GHz transmitter output generates -3.5 dBm, while the 82.5-GHz differential output power is +2.5 dBm. This transceiver occupies 840 mum times 1365 mum, is biased from 3.3 V, and consumes 0.9 W. Two stand-alone 5-stage amplifiers, centered at 140 GHz and 170 GHz, were also fabricated showing 17 dB and 15 dB gain at 140 GHz and 170 GHz, respectively. The saturated output power of the amplifiers is +1 dBm at 130 GHz and 0 dBm at 165 GHz. All circuits were characterized over temperature up to 125degC. These results demonstrate for the first time the feasibility of SiGe BiCMOS technology for circuits in the 100-180-GHz range.

Phase reduction of stochastic limit cycle oscillators.

Abstract: We point out that for an oscillator subjected to noise the conventional phase equation is not a proper approximation even for weak noise We present a phase reduction method valid for an oscillator subjected to weak white Gaussian noise Numerical evidence demonstrates that the phase equation properly approximates dynamics of the original oscillator Moreover, we show that, in general, noise causes a shift of the oscillator frequency and discuss its effects on entrainment

A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology

Abstract: The design and experimental verification of a 75-GHz phase-locked loop (PLL) fabricated in 90-nm CMOS technology is presented. The circuit incorporates a three-quarter wavelength oscillator to achieve high-frequency operation and a novel phase-frequency detector (PFD) based on SSB mixers to suppress the reference feedthrough. The PLL demonstrates an operation range of 320 MHz and reference sidebands of less than -72 dBc while consuming 88 mW from a 1.45-V supply.

A Wide-Band CMOS LC VCO With Linearized Coarse Tuning Characteristics

Abstract: A pseudo-exponential capacitor bank structure is proposed to implement a wide-band CMOS LC voltage-controlled oscillator (VCO) with linearized coarse tuning characteristics. An octave bandwidth VCO employing the proposed 6-bit pseudo-exponential capacitor bank structure has been realized in 0.18-mum CMOS. Compared to a conventional VCO employing a binary weighted capacitor bank, the proposed VCO has considerably reduced the variations of the VCO gain (K VCO) and the frequency step per a capacitor bank code (f step/code) by 2.7 and 2.1 times, respectively, across the tuning range of 924-1850 MHz. Measurement results have also shown that the VCO provides the phase noise of - 127.1 dBc/Hz at 1-MHz offset for 1.752-GHz output frequency while dissipating 6 mA from a 1.8-V supply.

A Low-Power Fully Monolithic Subthreshold CMOS Receiver With Integrated LO Generation for 2.4 GHz Wireless PAN Applications

Abstract: This paper reports a fully monolithic subthreshold CMOS receiver with integrated subthreshold quadrature LO chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage boosting, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling have been combined to lower the total power consumption. The subthreshold receiver, consisting of the switched-gain low noise amplifier, the quadrature mixers, and the variable gain amplifiers, consumes only 1.4 mW of power and has a gain of 43 dB and a noise figure of 5 dB. The entire quadrature LO chain, including a stacked quadrature VCO and differential cross-coupled buffers, also operates in the subthreshold region and consumes a total power of 1.2 mW. The subthreshold receiver with integrated LO generation is implemented in a 0.18 mum CMOS process. The receiver has a 3-dB IF bandwidth of 95 MHz.

Design and Analysis of CMOS Subharmonic Injection-Locked Frequency Triplers

Abstract: K- and V-band CMOS differential subharmonic injection-locked frequency triplers (ILFTs) are proposed, analyzed, and designed. Based on the proposed ILFT structure, models for the injection-locking range and the output phase noise are developed. A K-band ILFT is designed and fabricated using 0.18-m standard CMOS technology. The measured injection-locking range is 1092 MHz with a dc power consumption of 0.45 mW and an input injection power of 4 dBm. The harmonic rejection ratios are 22.65, 30.58, 29.29, 40.35 dBc for the first, second, fourth, and fifth harmonics, respectively. The total injection-locking range of the -band ILFT can achieve 3915 MHz when the varactors are used and the dc power consumption is increased to 2.95 mW. A -band ILFT is also designed and fabricated using 0.13-m standard CMOS technology. The measured injection-locking range is 1422 MHz with 1.86-mW dc power consumption and 6-dBm input injection power. The injection-locking range of the proposed ILFT is similar to the tuning range of a conventional varactor-tuned bulk-CMOS voltage-controlled oscillator (VCO). Moreover, the proposed ILFT has a greater output power and a lower dc power consumption level than a VCO. As a result, it is feasible to use the proposed ILFT in low-power millimeter-wave synthesizers.

A 95GHz Receiver with Fundamental-Frequency VCO and Static Frequency Divider in 65nm Digital CMOS

Abstract: This paper presents a fully integrated receiver, with LNA, mixer, IF amplifier, fundamental-frequency quadrature VCO, and static frequency divider, operating at 95GHz in a 65nm general-purpose (GP) CMOS technology. The receiver consumes 206mW from a 1.2V/1.5V supply. With large RF and IF bandwidths of over 19GHz and 16GHz, respectively, it is suitable for passive-imaging applications, and for wireless chip-to-chip communication at data-rates exceeding 20Gb/s. Together with the recently reported 60GHz receiver in 90nm CMOS, this 95GHz receiver in 65nm CMOS demonstrates that scaling of entire mm-wave receivers is possible in both frequency coverage and across technology nodes.

A 16–18.8-GHz Sub-Integer-N Frequency Synthesizer for 60-GHz Transceivers

Abstract: An 18-GHz range frequency synthesizer is implemented in 0.13-mum SiGe BiCMOS technology as part of a 60-GHz superheterodyne transceiver chipset. It provides for RF channels of 56.5-64 GHz in 500-MHz steps, and features a phase-rotating multi-modulus divider capable of sub-integer division. Output frequency range from the synthesizer is 16.0 to 18.8 GHz, while the enabled RF frequency range is 3.5 times this, or 55.8 to 65.8 GHz. The measured RMS phase noise of the synthesizer is 0.8deg (1 MHz to 1 GHz integration), while phase noise at 100-kHz and 10-MHz offsets are -90 and -124 dBc/Hz, respectively. Reference spurs are 69 dBc; sub-integer spurs are -65 dBc; and combined power consumption from 1.2 and 2.7 V is 144 mW.

A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN

Abstract: This paper introduces a fully integrated 2x2 two-stream MIMO radio SoC that integrates all of the functions of an 802.11n WLAN. The 0.13 mum CMOS radio SoC, which integrates two dual-band (2.4 GHz and 5 GHz) RF transceivers, analog baseband filters, data converters, digital physical layer, media access controller, and a PCI Express interface, provides a low-cost low-power small-form-factor WLAN solution. The MIMO radio comprises two identical dual-band transceivers that share a common frequency synthesizer capable of operating in both integer-N and fractional-N modes. In 2.4 GHz mode, the transceiver uses a direct-conversion architecture with a 3.2 GHz fractional-N frequency synthesizer. Direct conversion is used primarily because of its simplicity and the area reduction it offers by eliminating the need for an IF path. A 3.2 GHz synthesizer frequency is used to avoid VCO pulling. The 3.2 GHz synthesizer output fvco is divided by two and then mixed with the original 3.2 GHz fvco to generate a 4.8 GHz frequency. This 4.8 GHz signal at twice the RF frequency is distributed to both transceivers. Within each transceiver, the 4.8 GHz signal is divided by two to generate the 2.4 GHz in-phase and quadrature LO signals. In the 5 GHz mode, the transceiver uses a sliding-IF dual-conversion architecture, in which the RF and IF LO signals are centered at 2/3 fRF and 1/3 fRF, respectively. The frequency synthesizer, operating in integer-N mode, thus provides a 3.2 GHz RF LO signal that is buffered and distributed to both transceivers. Within each transceiver a resistively loaded divide-by-two circuit is used to generate the quadrature LO signals at 1/3 fRF. The channel center frequencies in the 5 GHz band allow integer-N operation of the synthesizer with a relatively high reference frequency, thus improving the phase noise.

A Time-Based Bandpass ADC Using Time-Interleaved Voltage-Controlled Oscillators

Abstract: In this paper, a bandpass analog-to-digital converter (ADC) based on time-interleaved oversampled ADC is introduced. Unlike previous delta-sigma bandpass ADCs that require accurate digital-to-analog converters and high-speed analog circuits, the proposed architecture provides bandpass function by time-interleaving first-order voltage-controlled-oscillator (VCO)-based ADCs. The use of VCO-based ADC has the advantage that its resolution is determined by the time resolution rather than the voltage resolution, thus making it attractive for future low-voltage CMOS processes. The performance of the proposed ADC is theoretically analyzed and simulated in ideal condition, as well as in nonideal condition, in the presence of nonlinearity, sampling clock jitter, and mismatch.

A 21 GHz Complementary Transformer Coupled CMOS VCO

Abstract: A new topology for low power voltage controlled oscillators (VCOs) using a 0.18-mum CMOS foundry process is presented in this letter. From the measured results, the VCO exhibits a tuning range of 3% at 21.3 GHz. Using complementary topology, the core power consumption and the output power are 9.6 mW and -3 dBm, respectively. With the broadside coupled transformer, the VCO achieves a good phase noise of -106 dBc/Hz at 1 MHz offset and a compact chip size of 350 times 470 mum2. It is the first time that the broadside coupled transformer approach is applied to transformer coupled CMOS VCOs.

A 600 $\mu$ W BAW-Tuned Quadrature VCO Using Source Degenerated Coupling

Abstract: A bulk-acoustic wave (BAW)-tuned quadrature voltage-controlled oscillator (BQVCO) designed in 0.13 mum CMOS is presented. The BQVCO operates at 2.1 GHz, with a power consumption of 600 muW at a 1 V supply. The oscillator achieves a phase noise of -143.5 dBc/Hz at 1 MHz offset with a figure of merit (FOM) of 212.1 dB. A new time-varying source degeneration coupling mechanism has been used to quadrature-couple the two oscillator cores for I/Q signal generation, reducing the required headroom of the series coupling transistors. A binary weighted capacitor array is designed for fine frequency tuning of the QVCO. For comparison, an identical QVCO with on-chip LC tank is fabricated, achieving a FOM of 179.7 dB.

A LiÉnard Oscillator Resonant Tunnelling Diode-Laser Diode Hybrid Integrated Circuit: Model and Experiment

Abstract: We report on a hybrid optoelectronic integrated circuit based on a resonant tunnelling diode driving an optical communications laser diode. This circuit can act as a voltage controlled oscillator with optical and electrical outputs. We show that the oscillator operation can be described by Lienard's equation, a second order nonlinear differential equation, which is a generalization of the Van der Pol equation. This treatment gives considerable insight into the potential of a monolithic version of the circuit for optical communication functions including clock recovery and chaotic source applications.

VCO design for 60 GHz applications using differential shielded inductors in 0.13 μm CMOS

Abstract: With the increasing interest in 60 GHz applications, low-cost CMOS circuit solutions emerge. The poor performance of CMOS devices at millimeter-wave frequencies complicates the design. In this work, we present two low-area VCOs covering the license-free 60 GHz band, using differential shielded (slow-wave) transmission line inductors. We discuss design and provide compact modeling of these inductors, compatible with stringent metal density rules of scaled CMOS. Measured phase noise below -90 dBc/Hz at 1 MHz offset is achieved, at a consumption of 3.9 mW at 1 V. The tuning range exceeds 10 %, for a tuning voltage restricted from ground to the supply.

A 24-GHz Receiver Frontend With an LO Signal Generator in 0.18- $\mu$ m CMOS

Abstract: Utilizing a standard 0.18-mum CMOS process, a receiver frontend and a local oscillator (LO) module are implemented for RF applications at the 24-GHz industrial, scientific, medical band. The proposed frontend is composed of a three-stage low-noise amplifier, a down-conversion mixer, and IF amplifiers. With an IF frequency of 4.82 GHz, the fabricated circuit demonstrates a conversion gain of 28.4 dB and a noise figure of 6.0 dB while maintaining an input return loss better than 14 dB. The measured P in - 1dB and IIP3 of the receiver frontend are -23.2 and -13.0 dBm, respectively. In addition, a circuit module, which generates the required dual down-conversion LO signals, is also included in this study. The proposed LO generator consists of a 19-GHz low-phase-noise voltage-controlled oscillator (VCO), a 4 : 1 frequency divider, and a quadrature phase-tuning circuit. From the measurement results, the VCO exhibits a tuning range of 850 MHz and a phase noise of -110 dBc/Hz at 1-MHz offset frequency. Operated at a supply voltage of 1.8 V, the current consumptions for the receiver frontend and the LO generator are both 30 mA.

A 1 V 2.2 mW 7 GHz CMOS Quadrature VCO Using Current-Reuse and Cross-Coupled Transformer-Feedback Technology

Abstract: A current-reused quadrature voltage-controlled oscillator (CR-QVCO) is proposed with the cross-coupled transformer-feedback technology for the quadrature signal generation. This CR-QVCO has the advantages of low-voltage/low-power operation with an adequate phase noise performance. A compact differential three-port transformer, in which two half-circle secondary coils are carefully designed to optimize the effective turn ratio and the coupling factor, is newly constructed to satisfy the need of signal coupling and to save the area consumption simultaneously. The quadrature oscillator providing a center frequency of 7.128 GHz for the ultrawideband (UWB) frequency synthesizer use is demonstrated in a 0.18 mum RF CMOS technology. The oscillator core dissipates 2.2 mW from a 1 V supply and occupies an area of 0.48 mm2. A tuning range of 330 MHz (with a maximum control voltage of 1.8 V) can be achieved to stand the frequency shift caused by the process variation. The measured phase noise is -111.2 dBc/Hz at 1 MHz offset from the center frequency. The IQ phase error shown is less than 2deg. The calculated figure-of-merit (FOM) is 184.8 dB.

Observation of injection locking in an optomechanical rf oscillator

Abstract: Injection locking of a radiation-pressure optomechanical oscillator is demonstrated through external modulation of the optical pump power near the optomechanical oscillation frequency. It is shown that the frequency and phase of a microtoroidal optomechanical oscillator can be locked to those of an electronic oscillator (or any other signal) that can modulate the optical input power and whose frequency is within the lock range.

A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS

Abstract: As CMOS scales down and grows more expensive, area-aware RF front-end design becomes appropriate. A wideband front-end is presented that uses an inductorless LNA and downconversion section up to 6 GHz. Frequency synthesis is realized using a single-inductor dual-band 3.5 and -10 GHz VCO. In-depth analysis describes the operation of the 4-port oscillator, and compares phase noise to that of a classical VCO. The front-end is realized in 90 nm digital CMOS. The LNA achieves a noise figure of 2.7 dB with an average IIP3 of -2 dBm. The dual-band VCO achieves a phase noise of -122 dBc/Hz and -128 dBc/Hz at 3.9 GHz and 10 GHz, respectively, at 2.5 MHz offset. Both circuits are embedded in a wideband direct-conversion front-end consuming less than 60 mW from a 1.2 V supply.