Showing papers on "Voltage-controlled oscillator published in 2009"

A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta\Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$ m CMOS

Abstract: The use of a VCO-based integrator and quantizer within a continuous-time (CT) ΔΣ analog-to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 μm CMOS with a measured performance of 81.2/78.1 dB SNR/SNDR over a 20 MHz bandwidth while consuming 87 mW from a 1.5 V supply and occupying an active area of 0.45 mm2 demonstrated. A key innovation is the explicit use of the oscillator's output phase to avoid the signal distortion that had severely limited the performance of earlier VCO-based ADCs, which had made use of its output frequency only. The proposed VCO-based integrator and quantizer structure enables fourth-order noise shaping with only three opamp-based integrators.

Voltage controlled oscillator, mmic, and high frequency wireless device

Abstract: A voltage controlled oscillator having low phase noise and including: a variable resonator including a varactor and a control voltage terminal; and an open-end stub connected in parallel to the variable resonator, the open-end stub having a length shorter than or equal to an odd multiple of one quarter of a wavelength of a harmonic signal plus one sixteenth of the wavelength of the harmonic signal, and longer than or equal to an odd multiple of one quarter of the wavelength of the harmonic signal minus one sixteenth of the wavelength of the harmonic signal. In this structure, a high Q value is realized for a fundamental wave frequency. Fluctuation in a control voltage due to a harmonic signal is controlled.

Wideband Multi-Mode CMOS VCO Design Using Coupled Inductors

Abstract: Coupled inductors can create multiple resonant frequencies in a compact high-order resonator. Together with proper nonlinear active circuitry, such a high-order resonator realizes a multi-mode oscillator covering a wide frequency range. Compared with conventional switched-resonator-based approaches that consume the same chip area, the proposed coupled-inductor-based resonator results in larger quality-factor, and hence, lower oscillator phase noise. In the proposed multi-mode oscillator that uses the multi-port coupled inductors, mode switching is achieved using independent active cores without using lossy switches in the resonator path. The behavior of the multi-mode resonator as a multi-port network in an oscillator, design trade-offs, and switching transient response of the multi-mode oscillator have been studied analytically. As a proof of concept, an integrated voltage-controlled oscillator (VCO) with a 1.28-6.06 GHz tuning range is designed and fabricated in a 0.13 mum CMOS technology. The triple-mode VCO uses a sixth-order resonator based on three coupled inductors with a compact common-centric layout. Depending on the oscillation frequency, the VCO current consumption is automatically adjusted from 2.9 to 6.1 mA to achieve a low phase noise throughout the frequency range. The measured phase noises at 1 MHz offset from carrier frequencies of 1.76, 2.26, 3.3, 4.5, and 5.6 GHz are -119.3 , -120.15 , -118.1 , -117 , and -113.5 dBc/Hz , respectively. The chip area, including the pads, is 1 mm times 1 mm and the supply voltage is 1.5 V.

A GHz spintronic-based RF oscillator

Abstract: A nano-sized oscillator for RF applications is presented which is based on two spintronic effects, the tunneling magnetoresistance (TMR) and the spin momentum transfer torque. The oscillation frequency is several GHz and can be tuned by both a DC bias current and an external DC magnetic field. High compactness, high tunability and full compatibility with standard CMOS process make this spin torque nano-oscillator (STNO) a promising candidate for future RF transceivers. The main issues to be addressed are spectral purity and output power. First measurements on a hybrid built connecting the STNO to a dedicated wideband amplifier show that today's performance in terms of power is close to but not yet compatible with telecommunication standard requirements. Using time domain analysis we show that frequency fluctuations are an issue for spectral purity. Frequency synthesis concepts based on STNOs are also discussed.

Progress and Challenges Towards Terahertz CMOS Integrated Circuits

Abstract: Key components of systems operating at high millimeter wave and sub-millimeter wave/terahertz frequencies, a 140-GHz fundamental mode voltage controlled oscillator (VCO) in 90-nm CMOS, a 410-GHz push-push VCO with an on-chip patch antenna in 45-nm CMOS, and a 125-GHz Schottky diode frequency doubler, a 50-GHz phase-locked loop with a frequency doubled output at 100 GHz, a 180-GHz Schottky diode detector and a 700-GHz plasma wave detector in 130-nm CMOS are demonstrated. Based on these, and the performance trends of nMOS transistors and Schottky diodes fabricated in CMOS, paths to terahertz CMOS circuits and systems including key challenges that must be addressed are suggested. The terahertz CMOS is a new opportunity for the silicon integrated circuits community.

Nanoscale CMOS Transceiver Design in the 90–170-GHz Range

Abstract: This paper reviews recent research conducted at the University of Toronto on the development of CMOS transceivers aimed at operation in the 90-170-GHz range. Unique nanoscale CMOS issues related to millimeter-wave circuit design in the 65-nm node and beyond are addressed with an emphasis on transistor and top-level layout issues, low-voltage circuit topologies, and design flow. A Doppler transceiver and two receivers fabricated in a 65-nm GPLP CMOS technology are described, along with a single pole, double throw antenna switch with better than 5-dB insertion loss and 25-dB isolation in the entire 110-170-GHz band. The first receiver has an IQ architecture with a fundamental frequency voltage-controlled oscillator, and is intended for wideband passive imaging applications at 100 GHz. The measured noise figure and downconversion gain are 7-8 and 10.5 dB, respectively, while the 3-dB bandwidth extends from 85 to 100 GHz. The second receiver has double-sideband architecture, operates in the 135-145-GHz range (the highest for CMOS receivers), and features an 8-dB gain LNA, a double-balanced Gilbert cell mixer, and a dipole antenna. The 90-94-GHz Doppler transceiver, the highest frequency reported to date in CMOS, is intended for the remote monitoring of respiratory functions. A Doppler shift of 30 Hz, produced by a slow-moving (4.8 cm/s) target located at a distance of 1 m, was measured with a transmitter output power of approximately + 2 dBm and a phase noise of -90 dBc/Hz at 1 MHz offset. The range correlation effect is demonstrated for the first time in CMOS by measuring the phase noise of the received baseband signal at 10-Hz offset, clearly indicating that 1/f noise has been canceled and it does not pose a problem in short-range applications, where neither a phase-locked loop nor a frequency divider are needed.

A 4.39–5.26 GHz LC-Tank CMOS Voltage-Controlled Oscillator With Small VCO-Gain Variation

Abstract: A wide band CMOS LC-tank voltage controlled oscillator (VCO) with small VCO gain (KVCO) variation was developed. For small KVCO variation, serial capacitor bank was added to the LC-tank with parallel capacitor array. Implemented in a 0.18 mum CMOS RF technology, the proposed VCO can be tuned from 4.39 GHz to 5.26 GHz with the VCO gain variation less than 9.56%. While consuming 3.5 mA from a 1.8 V supply, the VCO has -113.65 dBc/Hz phase noise at 1 MHz offset from the carrier.

SiGe Bipolar VCO With Ultra-Wide Tuning Range at 80 GHz Center Frequency

Abstract: A SiGe millimeter-wave VCO with a center frequency around 80 GHz and an extremely wide (continuous) tuning range of 24.5 GHz ( ap 30%) is presented. The phase noise at 1 MHz offset is -97 dBc/Hz at the center frequency (and less than -94 dBc/Hz in a frequency range of 21 GHz). The maximum total output power is about 12 dBm. A cascode buffer improves decoupling from the output load at reasonable VCO power consumption (240 mW at 5 V supply voltage). A low-power frequency divider (operating up to 100 GHz) provides, in addition, a divided-by-four signal. As a further intention of this paper, the basic reasons for the limitation of the tuning range in millimeter-wave VCOs are shown and the improvement by using two (instead of one) varactor pairs is demonstrated.

A 0.13µm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based integrator and quantizer

Abstract: Voltage-controlled oscillator (VCO) based ADCs have become a topic of great interest due to the unique and attractive signal-processing properties they offer in the design of oversampling converters. Assuming a ring-oscillator structure, the outputs of a VCO toggle between two discrete levels (V DD and GND) like a CMOS digital gate, enabling simple multibit quantization using D-flip-flops. Since only one VCO output phase transitions at a given sampling instant while all others saturate to the positive/negative supply, quantization is robust to flip-flop voltage offsets and metastability, and has guaranteed monotonicity. Furthermore, the VCO behaves as a CT integrator in that its output phase is proportional to the time integral of the applied control voltage. As long as it oscillates, the VCO output phase accumulates endlessly, implying that it is also an integrator with infinite DC gain.

Design and Analysis of a 90 nm mm-Wave Oscillator Using Inductive-Division LC Tank

Abstract: A 60 GHz voltage-controlled oscillator with an inductive division LC tank has been designed in 90 nm CMOS. The analysis of the oscillator shows that the presence of higher harmonics, the capacitance nonlinearity and the very high K VCO are critical for the phase noise performance of oscillators. Therefore, a pseudo-differential amplifier is employed in this design because of its high linearity. Furthermore, the proposed inductive division reduces the phase noise by increasing the signal amplitude across the varactor, without affecting the operation mode of the cross-coupled pair transistors. It also helps to increase the tuning range by isolating the varactor from the parasitic capacitances of the transistors and interconnects. The mm-wave oscillator is fabricated in a 90 nm CMOS technology. Under 0.7 V supply, the oscillator achieves a tuning range from 53.2 GHz to 58.4 GHz, consuming 8.1 mW. At 58.4 GHz, the phase noise is -91 dBc/Hz at 1 MHz offset. Under 0.43 V supply, the oscillator achieves a tuning range from 58.8 to 61.7 GHz. At 61.7 GHz, the phase noise is -90 dBc/Hz @1& MHz offset with a power consumption of only 1.2 mW.

Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers

Abstract: An LC-VCO based phase-locked loop (PLL) frequency synthesizer which incorporates loop bandwidth tracking is described. In order to minimize loop bandwidth variations resulting from changes in the LC-VCO gain, the proposed PLL employs an averaging varactor based split-tuned LC-VCO and a servo loop which sets the charge-pump current to be inversely proportional to the square of the oscillation frequency. The combination of these techniques maintains a constant loop bandwidth over a wide range of operating frequencies. Fabricated in a 0.13 mum CMOS technology, the prototype chip measures less than plusmn4% variation in KVCOmiddotICP / N (equivalent to the variation in PLL loop bandwidth) for an operating frequency range of 3.1 to 3.9 GHz.

A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator With Coarse and Fine Frequency Tuning

Abstract: A 7-GHz CMOS voltage controlled ring oscillator that employs multiloop technique for frequency boosting is presented in this paper. The circuit permits lower tuning gain through the use of coarse/fine frequency control. The lower tuning gain also translates into a lower sensitivity to the voltage at the control lines. Fabricated in a standard 0.13-mum CMOS process, the proposed voltage-controlled ring oscillator exhibits a low phase noise of -103.4 dBc/Hz at 1 MHz offset from the center frequency of 7.64 GHz, while consuming a current of 40 mA excluding the buffer.

A Two-Stage Ring Oscillator in 0.13- $\mu{\hbox{m}}$ CMOS for UWB Impulse Radio

Abstract: We present a two-stage digitally controlled ring oscillator designed mainly for impulse-radio ultra-wideband (UWB) applications. Each basic stage utilizes a local positive feedback, allowing to achieve steady oscillation at low current consumption levels, and to extend the frequency tuning over an ultra-wide range. The frequency tuning is achieved via the control of the tail resistor in each stage. The circuit is fabricated in a 0.13-mum CMOS technology. It features full UWB coverage at slightly higher than 1.3-V supply voltage, -121.7-dBc/Hz phase noise at a 5.6-GHz carrier, and 10-MHz offset, and less than 5-mW power consumption for the digitally controlled oscillator core alone at 10.18-GHz maximum frequency under 1.3-V supply voltage.

CMOS Oscillators for Clock Distribution and Injection-Locked Deskew

Abstract: The distribution and alignment of high-frequency clocks across a wide bus of links is a significant challenge in modern computing systems. A low power clock source is demonstrated by incorporating a buffer into a cross-coupled oscillator. Because the load is isolated from the tank, the oscillator can directly drive 50-Ohm impedances or large capacitive loads with no additional buffering. Using this topology, a quadrature VCO (QVCO) is implemented in 0.13 mum digital CMOS. The QVCO oscillates at 20 GHz, consumes 20 mW and provides 12% tuning range. The measured phase noise is -101 dBc/Hz @ 1 MHz frequency offset. A clock alignment technique based upon injection-locked quadrature-LC or ring oscillators is then proposed. Although injection-locked oscillators (ILOs) are known to be capable of deskewing and jitter filtering clocks, a study of both LC and ring ILOs indicates significant variation in their jitter tracking bandwidth when used to provide large phase shifts. By selectively injecting different phases of a quadrature-LC or ring VCO, this problem is obviated resulting in reduced phase noise. The technique is demonstrated using a LC QVCO at 20 GHz while burning only 20 mW of power and providing an 8 dB improvement in phase noise. A ring oscillator deskews a 2 to 7 GHz clock while consuming 14 mW in 90 nm CMOS.

A 95nW ring oscillator-based temperature sensor for RFID tags in 0.13µm CMOS

Abstract: In this paper, a ring oscillator-based CMOS temperature sensor with nano-watt power consumption is presented for RFID applications. Unlike conventional temperature sensors based on bandgap reference and ADC that consume large amount of power, the proposed sensor exploits the temperature dependence of the threshold voltage and carrier mobility of MOS transistors that affect the frequency of a ring oscillator. In order to maximize the temperature sensitivity and dynamic range, a supply voltage of 0.3V is used, which allows the oscillator to operate in subthreshold, near-threshold and above threshold region under different temperature conditions. In order to handle process variation, the frequency of the oscillator can be digitally trimmed by both a capacitor bank and stacked transistors. Measured data from 0.13-µm CMOS test chips indicate that the proposed temperature sensor has a resolution of 0.4°C/LSB with a 10-bit digital output code over a temperature range of 8°C to 85°C. At 10Hz of sampling frequency, the proposed sensor consumes 95nW and occupies 0.04mm2.

Time domain measurement of phase noise in a spin torque oscillator

Abstract: We measure oscillator phase from the zero crossings of the voltage vs. time waveform of a spin torque nanocontact oscillating in a vortex mode. The power spectrum of the phase noise varies with Fourier frequency $f$ as $1/f^2$, consistent with frequency fluctuations driven by a thermal source. The linewidth implied by phase noise alone is about 70 % of that measured using a spectrum analyzer. A phase-locked loop reduces the phase noise for frequencies within its 3 MHz bandwidth.

Low Phase-Noise Planar Oscillators Employing Elliptic-Response Bandpass Filters

Abstract: In this paper, a low phase-noise planar oscillator employing an elliptic bandpass filter as a frequency stabilization element within its feedback loop is presented. The oscillator phase noise is significantly reduced by taking advantage of the group-delay peaks formed at the passband edges of the elliptic filter. A filter optimization technique for low phase-noise oscillator designs is introduced and applied to a four-pole bandpass elliptic filter. An X-band oscillator using the optimized filter in the feedback loop is designed and tested. At the oscillation frequency of 8.05 GHz, the measured phase noise is -143.5 dBc/Hz at 1-MHz offset frequency. The oscillator exhibits an output power of 3.5 dBm with an dc-RF efficiency of 10%. To the authors' best knowledge, this is the lowest phase noise performance for an X-band planar microwave oscillator.

A 0.65-V 2.5-GHz Fractional-N Synthesizer With Two-Point 2-Mb/s GFSK Data Modulation

Abstract: We present ultra-low-voltage circuit design techniques for a fractional-N RF synthesizer with two-point modulation which was realized in 90-nm CMOS using only regular VT devices.; the voltage controlled oscillator, phase-frequency detector and charge pump operate from a 0.5 V supply while the divider uses a 0.65 V supply. The frequency synthesizer achieves a phase noise better than -120 dBc/Hz at 3 MHz, while consuming 6 mW. A calibration technique to equalize the gain between the two modulation ports is introduced and enables phase/frequency modulation beyond the loop bandwidth of the phase-locked loop. Measurement results for 2-Mb/s GFSK modulation are presented.

A 1.94 to 2.55 GHz, 3.6 to 4.77 GHz Tunable CMOS VCO Based on Double-Tuned, Double-Driven Coupled Resonators

Abstract: This paper presents a multi-band CMOS VCO using a double-tuned, current-driven transformer load. The dual frequency range oscillator is based on enabling/disabling the driving current in the secondary port of the transformer. This approach eliminates the effect of switches connected directly to the VCO tank whose capacitance and on-resistance affect both the tuning range and the phase noise of a typical multi-band oscillator. The relation between the coupling coefficient of the transformer load, selection of frequency bands, and the resulting quality factor at each band is investigated. The concept is validated through measurement results from a prototype fabricated in 0.25 ?m CMOS technology. The VCO has a measured tuning range of 1.94 to 2.55 GHz for the low frequency range and 3.6 to 4.77 GHz for the high frequency range. It draws a current of 1 mA from 1.8 V supply with a measured phase noise of -116 dBc/Hz at 1 MHz offset from a 2.55 GHz carrier. For the high frequency band, the VCO draws 10.1 mA from the same supply with a phase noise of -122.8 dBc/Hz at 1 MHz offset from a 4.77 GHz carrier.

A BiCMOS Dual-Band Millimeter-Wave Frequency Synthesizer for Automotive Radars

Abstract: Design and implementation of a millimeter-wave dual-band frequency synthesizer, operating in the 24 GHz and 77 GHz bands, are presented. All circuits except the voltage controlled oscillators are shared between the two bands. A multi-functional injection-locked circuit is used after the oscillators to simplify the reconfiguration of the division ratio inside the phase-locked loop. The 1 mm times 0.8 mm synthesizer chip is fabricated in a 0.18 mum silicon-germanium BiCMOS technology, featuring 0.15 mum emitter-width heterojunction bipolar transistors. Measurements of the prototype demonstrate a locking range of 23.8-26.95 GHz/75.67-78.5 GHz in the 24/77 GHz modes, with a low power consumption of 50/75 mW from a 2.5 V supply. The closed-loop phase noise at 1 MHz offset from the carrier is less than -100 dBc/Hz in both bands. The frequency synthesizer is suitable for integration in direct-conversion transceivers for K/W-band automotive radars and heterodyne receivers for 94 GHz imaging applications.

A Dual-Band CMOS Voltage-Controlled Oscillator Implemented With Dual-Resonance LC Tank

Abstract: A new fully integrated, dual-band CMOS voltage controlled oscillator (VCO) is presented. The VCO is composed of n-core cross-coupled Colpitts VCOs and was implemented in 0.18 mum CMOS technology with 0.8 V supply voltage. The circuit allows the VCO to operate at two resonant frequencies with a common LC tank. The VCO has two control inputs, one for continuous control of the output frequency and one for band switching. This VCO is configured with 5 GHz and 12 GHz frequency bands with differential outputs. The dual-band VCO operates in 4.78-5.19 GHz and 12.19-12.61 GHz. The phase noises of the VCO operating at 5.11 and 12.2 GHz are -117.16 dBc/Hz and -112.15 dBc/Hz at 1 MHz offset, respectively, while the VCO draws 3.2/2.72 mA and 2.56/2.18 mW consumption at low/high frequency band from a 0.8 V supply.

Configurable digital-analog phase locked loop

Abstract: A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.

Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study

Abstract: This paper proposes a novel flow for parasitic and process-variation aware design of radio-frequency integrated circuits (RFICs). A nano-CMOS current-starved voltage controlled oscillator (VCO) circuit has been designed using this flow as a case study. The oscillation frequency is considered as the objective optimization function with the area overhead as constraint. Extensive Monte Carlo simulations have been carried out on the parasitic extracted netlist of the VCO to study the effect of process variation on the oscillation frequency. In the design cycle, a performance degradation of 43.5% is observed when the parasitic extracted netlist is subjected to worst-case process variation. The proposed design flow could bring the oscillation frequency within 4.5% of the target, leading to convergence of the complete design in only one design iteration. To the best of the authors' knowledge, this paper presents the first work focussed on a current starved VCO in which the combined effect of parasitics and process variations has been considered.

Method and system for an integrated voltage controlled oscillator-based transmitter and on-chip power distribution network

Abstract: Methods and systems for an integrated voltage controlled oscillator (VCO)-based transmitter and on-chip power distribution network are disclosed and may include supplying bias voltages and/or ground to a chip utilizing conductive lines. One or more VCOs and low-noise amplifiers (LNAs) may each be coupled to a leaky wave antenna (LWA) integrated in the bias voltage and/or ground lines. One or more clock signals may be generated utilizing the VCOs, which may be transmitted from the LWAs coupled to the VCOs, to the LWAs coupled to the LNAs. RF signals may be transmitted via the LWAs, and may include 60 GHz signals. The LWAs may include microstrip and/or coplanar waveguides, where a cavity length of the LWAs may be dependent on a spacing between conductive lines in the waveguides. The LWAs may be dynamically configured to transmit the clock signals at a desired angle from a surface of the chip.

A 2.2GHz 7.6mW sub-sampling PLL with −126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18µm CMOS

Abstract: A clock with low phase-noise/jitter is a prerequisite for high-performance ADCs, wireline and optical data links and radio transceivers. This paper presents a 2.2GHz clock-generation PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. The PLL does not need frequency divider in locked state and achieves a low in-band phase noise values at low power.

A 140-GHz double-sideband transceiver with amplitude and frequency modulation operating over a few meters

Abstract: This paper describes the first demonstration of Doppler detection and data transmission at 140 GHz and 4 Gb/s through the air using a single-chip silicon transceiver at 140 GHz. The transceiver, which consists of a 140-GHz push-push VCO with a static divide-by-64 chain, a 140-GHz amplitude modulator, a 140-GHz LO amplifier, a fundamental frequency mixer, a 140-GHz LNA, and a variable gain IF amplifier, has a downconversion gain of 30 dB and a noise figure of 12.3 dB. It is fabricated in a 130-nm SiGe BiCMOS technology, occupies an area of 1.44 mm2, and consumes 1.5 W.

A 10MHz 80μW 67 ppm/°C CMOS reference clock oscillator with a temperature compensated feedback loop in 0.18μm CMOS

Abstract: A 10MHz, 80μW CMOS reference clock oscillator is presented in 0.18μm CMOS. The proposed oscillator employs a supply-regulated ring-oscillator in a temperature compensated feedback loop, which minimizes the frequency sensitivity to supply and temperature variations. The clock oscillator achieves frequency variation of less than ±0.05% against supply variation of 1.2V ~ 3V and ±0.4% against temperature variation of −20°C ~ 120°C. In addition, low power consumption is achieved by using sub-threshold bias circuits.

Improvements in or relating to radio receivers

Abstract: A radio receiver comprises an input (14) for a modulated radio frequency signal, a frequency down converter (16) coupled to the input, the frequency down converter including quadrature mixers (32,34) for demodulating a received modulated radio frequency signal using a local oscillator signal. An analogue-to-digital converter (54, 56) is coupled to receive demodulated signalsfrom the mixing means. The analogue-to-digital converter, which may comprise a continuous time sigma delta converter, has an input for a sampling clock frequency(f s ). A voltage controlled oscillator (38) providesthe local oscillator signaland supplies afrequency divider(60, 94) used to providethe sampling clock frequency.The dividing ratio (1/A) of the frequency divideris variablein response to variations in the strength of an 15 output signal from the digital-to-frequency converter and the variations in the frequency of the sampling clock frequencyvary the gain of the analogue-to- frequency converterthereby providing automatic gain control.

Low Phase Noise G $ _{m}$ -Boosted Differential Gate-to-Source Feedback Colpitts CMOS VCO

Abstract: This paper presents a g m-boosted differential gate-to-source feedback Colpitts (GS-Colpitts) CMOS voltage-controlled oscillator (VCO) that consumes a lower oscillation start-up current. The proposed architecture allows a wider range of saturation mode operation for the switching transistors, which helps suppress AM-to-FM conversion by these transistors. In addition, the phase noise contribution of the flicker noise in the switching transistor is reduced through the capacitor feedback network of the Colpitts oscillator. As a result, the proposed topology can achieve better phase noise performance and a higher figure of merit (FOM) compared to a conventional NMOS-only cross-coupled VCO. The proposed VCO is implemented in a 0.18-mum CMOS for 1.78 to 1.93 GHz operation. At 1.86 GHz, the measurements show phase noise of -105 and -128 dBc/Hz (corresponding to FOM = 191.2) at offsets of 100 kHz and 1 MHz, respectively, while dissipating 1.8 mA from a 0.9-V supply.

A 0.114-mW dual-conduction class-C CMOS VCO with 0.2-V power supply

Abstract: This paper proposes a dual-conduction class-C CMOS VCO for ultra-low supply voltages. Two cross-coupled NMOS pairs with different bias points are employed, which realize impulselike current waveform to improve the phase noise in the low supply conditions. The proposed VCO was implemented in a standard 0.18 μm CMOS technology, which oscillates at a carrier frequency of 4.5GHz with a 0.2-V supply voltage. The measured phase noise is −104 dBc/Hz@1MHz-offset with a power consumption of 114 μW, and FoM is −187 dBc/Hz.