Showing papers on "Voltage-controlled oscillator published in 2010"

Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter

Abstract: A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time-based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This paper analyzes the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, design criteria for determining parameters for VCO-based ADCs are described. In addition, a digital calibration technique to enhance the spurious-free dynamic range degraded by the nonlinearity is also introduced. To verify the theoretical analysis, a prototype chip is implemented in a 0.13-?m CMOS process. With a 500-MHz sampling frequency, the prototype achieves a signal-to-noise ratio ranging from 71.8 to 21.3 dB for an input bandwidth of 100 kHz-247 MHz, while dissipating 12.6 mW and occupying an area of 0.078 mm2.

A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC

Abstract: This paper presents a reconfigurable continuous-time delta-sigma modulator for analog-to-digital conversion that consists mostly of digital circuitry. It is a voltage-controlled ring oscillator based design with new digital background calibration and self-cancelling dither techniques applied to enhance performance. Unlike conventional delta-sigma modulators, it does not contain analog integrators, feedback DACs, comparators, or reference voltages, and does not require a low-jitter clock. Therefore, it uses less area than comparable conventional delta-sigma modulators, and the architecture is well-suited to IC processes optimized for fast digital circuitry. The prototype IC is implemented in 65 nm LP CMOS technology with power dissipation, output sample-rate, bandwidth, and peak SNDR ranges of 8-17 mW, 0.5-1.15 GHz, 3.9-18 MHz, and 67-78 dB, respectively, and an active area of 0.07.

An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback

Abstract: An on-chip CMOS relaxation oscillator with voltage averaging feedback using a reference proportional to supply voltage is presented. A voltage-averaging feedback (VAF) concept is proposed to overcome conventional relaxation oscillator problems such as sensitivity to comparator delay, aging, and flicker noise of current sources. A test-chip with typical frequency of 14.0 MHz was fabricated in a 0.18 μm standard CMOS process and measured frequency variations of ±0.16 % for supply changes from 1.7 to 1.9 V and ±0.19% for temperature changes from -40 to 125°C. The prototype draws 25 μA from a 1.8 V supply, occupies 0.04 mm2, and achieves 7x reduction in accumulated jitter (at 1500th cycle) as compared to a oscillator without VAF.

A millimeter-wave intra-connect solution

Abstract: A novel millimeter-wave Intra-Connect solution for short range, high speed, internal I/O connections in low-power logic 40 nm CMOS process is demonstrated. The system consists of a transmitter and a receiver that uses binary amplitude shift keying (ASK) modulation for a compact and power efficient design. The receiver realizes coherent demodulation using injection locking without a PLL or an external reference clock utilizing a path to inject the received signal into the VCO. The demonstrator achieves 11 Gb/s ASK data transmission over 14 mm using bond-wire antennas with a bit error rate (BER) of less than 10-11. The active footprint of the transmitter is 0.06 mm2 and the power consumption is 29 mW with an energy usage of 6.4 pj/bit per channel. The receiver occupies the active footprint of 0.07 mm2 and consumes 41 mW. The work shows the feasibility of the millimeter-wave Intra-Connect for high speed internal I/O connections.

Analysis and Design of an Ultralow-Power CMOS Relaxation Oscillator

Abstract: This paper presents the design of a low-voltage ultralow-power relaxation oscillator without external components. The application field for this oscillator is the clock generation of low-power wake-up functions for battery-operated systems. A detailed analysis of the oscillator, including the temperature performance, is derived and verified with experimental results. The oscillator operates at a typical frequency of 3.3 kHz and consumes 11 nW from a 1-V supply at room temperature, and a temperature drift of less than 500 ppm/°C is achieved over the temperature range of -20°C to 80°C. An efficient design implementation has resulted in a cell area of 0.1 mm2 in a standard 0.35- μm digital CMOS technology.

Phase Noise in LC Oscillators: A Phasor-Based Analysis of a General Result and of Loaded $Q$

Abstract: Recent work by Bank, and Mazzanti and Andreani has offered a general result concerning phase noise in nearly-sinusoidal inductance-capacitance (LC) oscillators; namely that the noise factor of such oscillators (under certain achievable conditions) is largely independent of the specific operation of individual transistors in the active circuitry. Both use the impulse sensitivity function (ISF). In this work, we show how the same result can be obtained by generalizing the phasor-based analysis. Indeed, as applied to nearly-sinusoidal LC oscillators, we show how the two approaches are equivalent. We analyze the negative-gm LC model and present a simple equation that quantifies output noise resulting from phase fluctuations. We also derive an expression for output noise resulting from amplitude fluctuations. Further, we extend the analysis to consider the voltage-biased LC oscillator and fully differential CMOS LC oscillator, for which the Bank's general result does not apply. Thus we quantify the concept of loaded Q.

Progress and Challenges Towards Terahertz CMOS Integrated Circuits

Abstract: Key components of systems operating at high millimeter wave and sub-millimeter wave/terahertz frequencies, a 140-GHz fundamental mode voltage controlled oscillator (VCO) in 90-nm CMOS, a 410-GHz push-push VCO with an on-chip patch antenna in 45-nm CMOS, and a 125-GHz Schottky diode frequency doubler, a 50-GHz phase-locked loop with a frequency doubled output at 100 GHz, a 180-GHz Schottky diode detector and a 700-GHz plasma wave detector in 130-nm CMOS are demonstrated. Based on these, and the performance trends of nMOS transistors and Schottky diodes fabricated in CMOS, paths to terahertz CMOS circuits and systems including key challenges that must be addressed are suggested. The terahertz CMOS is a new opportunity for the silicon integrated circuits community.

Regulating power consumption of digital circuitry using a multi-layer ring oscillator

Abstract: A computing device is disclosed comprising digital circuitry fabricated on a multi-layer integrated circuit including a first layer and a second layer, and a multi-layer ring oscillator operable to generate a propagation delay frequency representing a propagation delay of the integrated circuit, wherein the multi-layer ring oscillator comprises a first interconnect fabricated on the first layer and a second interconnect fabricated on the second layer. The propagation delay frequency is compared to a reference frequency to generate a frequency error, and at least one of a supply voltage and a clocking frequency applied to the digital circuitry is adjusted in response to the frequency error.

Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

Abstract: This paper presents phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-sampling phase detector (SSPD) (which is also referred to as a sampling phase detector). The VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the sampling at the reference frequency. The underlying VCO sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 μm CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is <; -80 dBc. The PLL consumes 3.8 mW while the in-band phase noise is -121 dBc/Hz at 200 kHz and the output jitter integrated from 10 kHz to 100 MHz is 0.3psrms.

Design of a 24-GHz CMOS VCO With an Asymmetric-Width Transformer

Abstract: A K-band CMOS voltage-controlled oscillator (VCO) is implemented with a 0.18- ?m radio frequency CMOS process. For low supply voltage operation, a transformer-feedback topology using a transformer is proposed. The analysis of the transformer-feedback VCO is presented. This shows that the inductance ratio of the transformer must be optimized, and asymmetric-width transformers allow the easy optimization and the high Q-factor. Based on this analysis, the transformer design consideration of the transformer feedback VCO is presented. The VCO operates at 24.27 GHz with the phase noise of -100.33 dBc/Hz at 1-MHz offset, and it consumes 7.8 mW from a 0.65-V supply voltage.

A Low Phase-Noise VCO Using an Electronically Tunable Substrate Integrated Waveguide Resonator

Abstract: In this paper, an X -band low phase-noise voltage-controlled oscillator (VCO) using a novel electronically tunable substrate integrated waveguide (SIW) resonator is proposed and developed for RF/microwave applications on the basis of the substrate integrated circuits concept. In this case, the resonant frequency of the SIW cavity resonator is tuned by different dc-biasing voltages applied over a varactor coupled to the cavity. Measured results show that the tuning range of the resonator is about 630 MHz with an unloaded Q U of 138. Subsequently, a novel reflection-type low phase noise VCO is developed by taking advantage of the proposed tunable resonator. Measured results demonstrate a frequency tuning range of 460 MHz and a phase noise of 88 dBc/Hz at a 100-kHz offset over all oscillation frequencies. The VCO is also able to deliver an output power from 6.5 to 10 dBm. This type of VCO is very suitable for low-cost microwave and millimeter-wave applications.

A 1–9 GHz Linear-Wide-Tuning-Range Quadrature Ring Oscillator in 130 nm CMOS for Non-Contact Vital Sign Radar Application

Abstract: A 1-9 GHz linear-wide-tuning-range quadrature ring oscillator has been designed and fabricated in UMC 0.13 ?m CMOS process. The chip was wire-bonded on printed circuit board and tested, showing a liner tuning range from 1 GHz to 9 GHz. Comparative study with other differential ring oscillators demonstrates the advantages of this design in low power consumption and linear-tuning. The oscillator was designed as the voltage controlled oscillator (VCO) for a non-contact vital sign radar sensor. It can also be used for other applications such as ultra-wideband (UWB) impulse radio and clock recovery in broadband optical communications.

Analytical Phase-Noise Modeling and Charge Pump Optimization for Fractional- $N$ PLLs

Abstract: We present an analytical frequency-domain phase-noise model for fractional-N phase-locked loops (PLLs). The model includes the noise of the crystal reference, the reference input buffer, the voltage-controlled oscillator (VCO), the loop filter, charge pump (CP) device noise, and sigma-delta modulator (SDM) noise, including its effect on the in-band phase noise. The thermal device noise of the CP and the turn-on time of the CP output current are found to be limiting the in-band phase noise of state-of-the-art synthesizers. Device noise considerations for bipolar transistors and MOSFETs suggest the use of CMOS-only CPs, even in BiCMOS technologies. We present a noise-optimized CMOS CP specifically designed for a dual-loop PLL architecture using two CPs. This PLL architecture keeps the dc output voltage of the noise-relevant CP and the phase-noise spectrum constant, regardless of temperature variations.

Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band

Abstract: Flicker noise up-conversion in voltage-biased oscillators can be effectively suppressed by inserting resistances in series to the drain of the transconductor MOSFETs. This solution avoids the degradation of the start-up margin and the adoption of area-demanding resonant filters with proper tuning. This paper presents a detailed theoretical analysis of 1/f noise up-conversion and quantitatively addresses the impact of two major contributions, namely the Groszkowski effect and the loop delay caused by stray capacitances at the drain node of the transistors. A simple flow for the design of an oscillator with suppressed flicker noise up-conversion is presented which is based on first-order closed-form formulas. Finally , theoretical estimates are compared to experimental results on a 65-nm CMOS VCO covering the 3.0-3.6 GHz band.

High Power-Supply-Rejection (PSR) Current-Mode Low-Dropout (LDO) Regulator

Abstract: Modern system-on-a-chip (SoC) solutions suffer from limited on-chip capacitance, which means that the switching events of functionally dense ICs induce considerable noise in the supplies. This ripple worsens the accuracy of sensitive analog electronics, such as ADCs, PLLs, and VCOs, etc. Without dropping a substantial voltage, point-of-load (PoL) low-dropout (LDO) regulators reduce (filter) this noise but only as much as their loop gains and bandwidths allow. This brief presents a 5-mA 1.5-μm bipolar current-mode LDO regulator that, with a higher bandwidth current loop, suppresses higher frequency noise by 49 dB (i.e., power-supply rejection) up to 10 MHz with only 68 nF at the output, which is 20 dB better than its voltage-mode counterpart.

A Fast and High-Precision VCO Frequency Calibration Technique for Wideband $\Delta \Sigma $ Fractional-N Frequency Synthesizers

Abstract: A VCO frequency calibration technique suitable for a wideband fractional-N PLL is presented. It provides a fast and high-precision search for an optimal discrete tuning curve of an LC VCO during the coarse tuning process in a fractional-N PLL. A high-speed frequency error detector (FED) converts the VCO frequency to a digital value and computes the exact frequency difference from a target frequency. A minimum error code finder finds an optimal code that is closest to the target frequency. Due to the pure digital domain operation, a ΔΣ modulator in PLL can be deactivated during the calibration process, which makes this technique fast and accurate especially for a ΔΣ fractional-N PLL. We achieve a single-bit calibration time of only kTREF for obtaining a frequency resolution of fREF/k, and compared to the conventional techniques, which is the best performance in terms of the calibration time versus resolution. Such fast VCO frequency calibration can greatly reduce the total lock time in a PLL. A 2.3-3.9 GHz fractional-N PLL employing the proposed calibration technique is implemented in 0.13 μm CMOS. Successful operation is verified through experimental results. The measured calibration time for a 6-bit capbank is 1.09 and 2.03 μs for a frequency resolution of 19.2 and 4.8 MHz, respectively.

A Current Reuse Quadrature GPS Receiver in 0.13 $\mu$ m CMOS

Abstract: A fully-integrated quadrature low-IF L1-band GPS receiver consumes only 6.4 mW in 0.13 μm CMOS. The RF front-end features a gate-modulated quadrature VCO for low phase noise and accurate quadrature phase signal generation. It merges the LNA, quadrature mixer, and quadrature VCO in a single current-reuse stacked topology that provides a conversion gain 42.5 dB with a power consumption of 1 mW. A continuous-time (CT) quadrature bandpass sigma-delta analog-to-digital converter (ADC) provides inherent anti-alias filtering, which simplifies the overall system. The second-order CT ΣΔ ADC achieves 65 dB dynamic range and dissipates only 4.2 mW using resistor DAC feedback. The receiver exhibits an NF of 6.5 dB and an IIP3 of - 30 dBm; the PLL phase noise is -110 dBc/Hz @ 1 MHz frequency offset with quadrature error less than 1°.

An Integrated 0.6–4.6 GHz, 5–7 GHz, 10–14 GHz, and 20–28 GHz Frequency Synthesizer for Software-Defined Radio Applications

Abstract: We present an integrated frequency synthesizer which is able to provide in-phase/quadrature phase signal over the frequency bands 0.6-4.6 GHz, 5-7 GHz, 10-14 GHz, and in-phase signal over 20-28 GHz for software-defined radio applications. An integrated voltage-controlled oscillator (VCO) with 34% tuning range and a set of high-speed dividers are used to accomplish all the frequencies. To achieve a wide tuning range while keeping a low gain and a low phase noise, the VCO employs digitally controlled sub-bands. The measured PLL phase noise is - 108 dBc/Hz, -121 dBc/Hz, and -135 dBc/Hz at 1 MHz offset for 24 GHz, 4 GHz, and 700 MHz, respectively. Fabricated in a 0.25 μm SiGe BiCMOS process, the synthesizer occupies a chip area of 4.8 mm2. The synthesizer was optimized for reconfigurable base station applications, but can also be used for cognitive radio, radar systems, satellite communication, and high-speed digital clock generation.

A 86 MHz–12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS

Abstract: A 86 MHz-12 GHz digital-intensive reconfigurable PLL frequency synthesizer is presented with 100 kHz to 2 MHz bandwidth. It leverages a 6 fJ/step 5.5 ps, 14b coarse-fine TDC and a 6-12 GHz dual-VCO set. Several simple calibration schemes are proposed that enable the proper performance of the highly efficient TDC in the PLL. The 0.28 mm2 synthesizer, which is appropriate for use in a Software-Defined Radio, features noise cancellation and digital phase modulation and consumes less than 30 mW.

On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures

Abstract: Performance variability in digital integrated circuits can largely affect parametric yield and product reliability in ultra deep submicrometer technologies. As a result, variation resilience is becoming an essential design requirement for future technology nodes, especially for timing critical applications. This paper proposes an on-chip variability sensor using phase-locked loop (PLL) to detect process, supply voltage (V DD), and temperature variations (process, voltage, and temperature variation) or even temporal reliability degradation stemming from negative bias temperature instability. Our analysis shows that control voltage (V cnt) of voltage-controlled oscillator in PLL can be used as a dynamic performance signature of an operating IC. Along with the proposed PLL-based sensor circuit, we also propose a variation-resilient system technique using adaptive body biasing (ABB). The PLL V cnt signal is efficiently transformed to an optimal body bias signal for various circuit blocks to avoid possible timing failures. Correspondingly, circuits can be designed with significantly relaxed timing constraint compared to conventional approaches, where a large amount of design resources can be wasted to take care of the worst-case situations. We demonstrated our approach on a test chip fabricated in IBM 130-nm CMOS technology. Measurement results show that the PLL-based sensor is cable of tracking various sources of circuit variations. Optimization analysis shows that 42% and 43% reduction in area and power can be obtained using our approach compared to the worst-case sizing. The proposed study refers to our previous study introduced in with major improvements in measurement results and analysis.

Injection-Locked CMOS Frequency Doublers for $\mu$ -Wave and mm-Wave Applications

Abstract: On-chip frequency generators for high frequency applications suffer from degradation of key passive components, variable capacitors in particular. In this framework, frequency multipliers can play a key role, allowing the design of voltage-controlled oscillators running at a frequency lower than required with advantage in terms of signal spectral purity and frequency tuning range. In this paper we present two injection locked frequency doublers for Ku-band and F-band applications respectively. Despite differences in implementation details, the same topology where a push-push pair injects a double frequency tone locking an autonomous differential oscillator is adopted. The circuits require limited input signal swing and provide a differential output over a broad frequency range. Dissipating 5.2 mW, the Ku-band multiplier, realized in a 0.13 μm CMOS node, displays an operation bandwidth from 11 GHz to 15 GHz with a peak voltage swing on each output of 470 mV. The F-band multiplier, realized in 65 nm CMOS technology, displays an operation bandwidth from 106 GHz to 128 GHz with a peak voltage swing on each output of 330 mV and a power dissipation of 6 mW. A prototype including the multiplier, driven by a half-frequency standard LC-tank VCO, demonstrates an outstanding 13.1% tuning range around 115 GHz.

Phase-Noise Analysis in Rotary Traveling-Wave Oscillators Using Simple Physical Model

Abstract: We show that the rotary traveling wave oscillator (RTWO) is well treated as a superposition of multiple standing-wave oscillators (SWOs). Based on the proposed physical interpretation, we derive a phase-noise formula for the SWO, and extend it to the RTWO, which can predict thermally induced phase noise with no more complexity than the well-understood LC voltage-controlled oscillator. Measurement and simulation validate the analysis. The physically based approach and simple resulting expressions make it possible to design the RTWO for a given phase noise without lengthy simulations.

A Subharmonic Receiver in SiGe Technology for 122 $~$ GHz Sensor Applications

Abstract: The iterative design of an integrated subharmonic receiver for 120-127 GHz is presented. The receiver consists of a single-ended low-noise amplifier (LNA), a push-push voltage-controlled oscillator (VCO) with 1/32 divider, a polyphase filter, and a subharmonic mixer. The receiver is fabricated in SiGe:C BiCMOS technology with fT/fmax of 255 GHz/315 GHz. In the first design the differential down-conversion gain of the receiver is 25 dB at 127 GHz, and the corresponding noise figure (NF) is 11 dB. The 3 dB bandwidth reaches from 125 GHz to 129 GHz. The input 1 dB compression point is at - 40 dBm. The receiver draws 139 mA from a supply voltage of 3.3 V. A subsequent design demonstrates 31 dB differential gain at 122 GHz, and 11 dB NF. The 3 dB bandwidth is from 121 GHz to 124 GHz. The receiver has a NF of 8 dB for 3 GHz IF frequency due to integrated RF bandpass-filtering. It is realized by the lower NF of the LNA, and the LNA itself.

Low Phase-Noise Planar Oscillators Based on Low-Noise Active Resonators

Abstract: A very low phase-noise planar X -band oscillator employing an active resonator has been demonstrated. The high frequency selectivity of the active filter, used as the resonator, is the key factor in phase-noise reduction. A design procedure to achieve the resonator's optimum performance for low phase-noise applications is presented. In particular, the effect of the excess noise introduced by the active filter is addressed and its impact on the oscillator's phase noise is minimized. The oscillator, operating at 8 GHz, shows a measured phase noise of -150 dBc/Hz at 1-MHz frequency offset with 10-dBm output power. To the best of our knowledge, this oscillator demonstrates the lowest phase noise among published X -band planar oscillators to date.

A Single-Chip CMOS UHF RFID Reader Transceiver for Chinese Mobile Applications

Abstract: UHF RFID reader transceiver for Chinese local standard (840-845 MHz and 920-925 MHz), in concord with the protocols of EPC Class-1 Gen-2 and ISO/IEC 18000-6C, is presented A highly linear RF front-end with low flicker noise, an on-chip self-jammer cancellation (SC) circuit with fast time-varying cut-off frequency and a DC-offset cancellation (DCOC) circuit are proposed to deal with the large self-jammer in the receiver In the presence of 22 dBm PA output power, the receiver achieves a sensitivity of -79 dBm including the 15 dB loss of the directional coupler A CMOS class-AB PA is integrated in the transmitter, with 22 dBm output power and 35% PAE The spectrum mask achieves ACPR1 of -45 dBc and ACPR2 of -60 dBc A sigma-delta fractional-N PLL with a single LC VCO is also implemented for good phase noise (-126 dBc/Hz @ 1 MHz offset) and high frequency resolution within 1 kHz This single-chip is fabricated in a 018 standard CMOS process It occupies a silicon area of 135 mm2 and dissipates 203 mW from a 18 V supply voltage when transmitting 75 dBm output power

A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback

Abstract: This paper introduces a continuous-time low-pass sigma-delta modulator operating with a seven-phase 400 MHz clocking scheme to control time-based processing in the 3-bit two-step quantizer and main digital-to-analog converter (DAC). An on-chip voltage-controlled oscillator and a complementary injection-locked frequency divider are utilized for low-jitter clock signal generation with multiple phases, allowing 3-bit pulse-width modulated feedback with a single-element DAC to avoid performance degradation from unit element mismatch problems associated with conventional multi-bit DACs. Fabricated in a standard 0.18 μm CMOS technology, the 5th-order modulator achieves a peak SNDR of 67.7 dB in 25 MHz bandwidth, consumes 48 mW from a 1.8 V supply, and occupies a die area of 2.6 mm2. The modulator has a measured SFDR of 78 dB and in-band IM3 under -72 dB with -2 dBFS two-tone signal power.

Injection-Locked CMOS Frequency Doublers for μ-Wave and mm-Wave Applications

Abstract: On-chip frequency generators for high frequency applications suffer from degradation of key passive components, variable capacitors in particular. In this framework, frequency multipliers can play a key role, allowing the design of voltage-controlled oscillators running at a frequency lower than required with advantage in terms of signal spectral purity and frequency tuning range. In this paper we present two injection locked frequency doublers for Ku-band and F-band applications respectively. Despite differences in implementation details, the same topology where a push-push pair injects a double frequency tone locking an autonomous differential oscillator is adopted. The circuits require limited input signal swing and provide a differential output over a broad frequency range. Dissipating 5.2 mW, the Ku-band multiplier, realized in a 0.13 μm CMOS node, displays an operation bandwidth from 11 GHz to 15 GHz with a peak voltage swing on each output of 470 mV. The F-band multiplier, realized in 65 nm CMOS technology, displays an operation bandwidth from 106 GHz to 128 GHz with a peak voltage swing on each output of 330 mV and a power dissipation of 6 mW. A prototype including the multiplier, driven by a half-frequency standard LC-tank VCO, demonstrates an outstanding 13.1 % tuning range around 115 GHz.

A Low-Phase-Noise Multi-Phase Oscillator Based on Left-Handed LC-Ring

Abstract: This paper presents a distributed multi-phase oscillator based on left-handed LC-ring. In contrast to traditional designs that couple multiple LC-tanks through MOSFETs, it uses an LC-ring as a single high-order resonator that generates multi-phase resonant signal. By avoiding coupling MOSFETs which deteriorate phase noise significantly, it can synthesize multiple phases while maintaining the same phase-noise figure-of-merit (FoM) as a single-stage LC oscillator. This also provides a systematic way of trading power for phase noise. The dynamics and the phase noise of the LC-ring oscillator are analyzed based on a mode-decomposition model. We also address the duality of left-/right-handed resonator in the context of oscillator in detail. These analysis was verified by prototypes in a 0.13 μm CMOS process with 0.5 V supply voltage: a four-stage LC-ring oscillator at 5.12 GHz draws 8 mA current and achieves a phase noise of -121.6 dBc/Hz@600 kHz, while a single-stage one at 5.34 GHz draws 2 mA and achieves -116.1 dBc/Hz@600 kHz. There is a good agreement among analysis, simulation, and measurement.

A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology

Abstract: The search for high speed, high bandwidth A/D converters is ongoing, and techniques to push the envelope are constantly being developed. In this paper an open loop, scalable, time-interleaved ADC architecture is presented, as well as a 60 GHz Colpitts oscillator. With the use of double-sampling, the timing skew requirements between channels is greatly relaxed, allowing sampling rates of up to 40 Gs/s at 4-bits of accuracy. This circuit is implemented using the IBM 8HP SiGe technology, with fT of 210 GHz. The performance of the 8HP ADC is validated by measurement. In addition, simulations with an experimental 8XP transistor model provided by IBM with a 350 GHz fT suggest that 30% more circuit speed is possible by just swapping the transistors.

A 90 GHz Hybrid Switching Pulsed-Transmitter for Medical Imaging

Abstract: This paper reports a fully integrated 90 GHz-carrier pulsed transmitter in 0.13 μm SiGe BiCMOS process for imaging applications. To obtain ultra-short programmable pulses, the transmitter employs a number of novel techniques including hybrid switching and Antentronics. The transmit path includes a quadrature VCO, PA driver, PA and the on-chip folded slot antenna. High speed ECL circuits generate and provide the short pulses in several operating modes. The transmitter achieves a record pulsewidth of 26 ps in the hybrid mode and 33 ps in the independent mode. This translates to >30 GHz of RF BW in the transmitter.