Showing papers on "Voltage-controlled oscillator published in 2011"

Wireless power feeder, wireless power receiver, and wireless power transmission system

Abstract: Power is fed from a feeding coil L2 to a receiving coil L3 by magnetic resonance. A VCO 202 alternately turns ON/OFF switching transistors Q1 and Q2 at a drive frequency fo, whereby AC power is fed to the feeding coil L2, and then the AC power is fed from the feeding coil L2 to the receiving coil L3. A phase detection circuit 114 detects a phase difference between the current phase and voltage phase, and the VCO 202 adjusts the drive frequency fo such that the phase difference becomes zero. When load voltage is changed, the detected current phase value is adjusted with the result that the drive frequency fo is adjusted.

A 300-GHz Fundamental Oscillator in 65-nm CMOS Technology

Abstract: Fundamental oscillators prove the existence of gain at high frequencies, revealing the speed limitations of other circuits in a given technology. This paper presents an oscillator topology that employs feedback from an output stage to the core, thus achieving a high speed. The behavior of the proposed oscillator is formulated and simulations are used to compare it with the conventional cross-coupled pair circuit. Three prototypes realized in 65-nm CMOS technology operate at 205 GHz, 240 GHz, and 300 GHz, each drawing 3.7 mW from a 0.8-V supply.

Gate speed regulator dithering ring oscillator to match critical path circuit

Abstract: A computing device is disclosed comprising digital circuitry including a critical path circuit, and a gate speed regulator. A ring oscillator generates an oscillation frequency, and dither circuitry periodically adjusts a number of inverter elements in the ring oscillator in order to adjust an average propagation delay of the ring oscillator relative to a propagation delay of the critical path circuit. A comparator compares the oscillation frequency to a reference frequency to generate an error signal, and an adjustable circuit, responsive to the error signal, adjusts at least one of a supply voltage and a clocking frequency applied to the digital circuitry.

Ensuring minimum gate speed during startup of gate speed regulator

Abstract: A computing device is disclosed comprising digital circuitry, and a gate speed regulator operable to generate a supply voltage applied to the digital circuitry. A frequency synthesizer generates a first reference frequency, and a propagation delay oscillator generates a first oscillation frequency in response to the supply voltage, wherein the first oscillation frequency is compared to the first reference frequency to generate a first error signal. A reference oscillator generates a second reference frequency in response to a reference voltage, and a startup oscillator generates a second oscillation frequency in response to the supply voltage, wherein the second oscillation frequency is compared to the second reference frequency to generate a second error signal. An adjustable circuit, responsive to the first and second error signals, adjusts the supply voltage applied to the digital circuitry.

A 90–240 MHz Hysteretic Controlled DC-DC Buck Converter With Digital Phase Locked Loop Synchronization

Abstract: This paper reports a digital phase locked loop (D-PLL) based frequency locking technique for high frequency hysteretic controlled dc-dc buck converters. The proposed converter achieves constant operating frequency over a wide output voltage range, eliminating the dependence of switching frequency on duty cycle or voltage conversion range. The D-PLL is programmable over a wide range of parameters and can be synchronized to a clock reference to ensure proper frequency lock and switching operation outside undesirable power supply resonance bands. The stability and loop dynamics of the proposed converter is analyzed using an analog equivalent PLL behavioral model which describes the dc-dc converter as a voltage-controlled oscillator (VCO). We demonstrate a 90-240 MHz single phase converter with fast hysteretic control and output conversion range of 33%-80%. The converter achieves an efficiency of 80% at 180 MHz, a load response of 40 ns for a 120 mA current step and a peak-to-peak ripple less than 25 mV. The circuit was implemented in 130 nm digital CMOS process.

High-Gain Fully Printed Organic Complementary Circuits on Flexible Plastic Foils

Abstract: We present several fully printed organic complementary circuits using n- and p-type organic thin-film transistors. n-Type and p-type devices are developed on a flexible polyethylene-naphthalate substrate. All organic layers are deposited using a low-cost screen-printing technique. The inverters show a high gain and a switching point at exactly VDD/2. A seven-stage voltage-controlled oscillator (VCO) is designed with an organic output buffer, using the n- and p-type organic transistors. This VCO oscillates at a frequency of 186 Hz. Finally, two complementary differential amplifiers with high gain and large bandwidth are presented. The amplifiers only draw a 1-μA current from a 40-V power supply.

A Low-Noise Quadrature VCO Based on Magnetically Coupled Resonators and a Wideband Frequency Divider at Millimeter Waves

Abstract: Wireless on-chip processing at millimeter waves still lacks key functions: quadrature generation enabling direct conversion architectures and simplifying phased-array systems, frequency division with an operating range wide enough to compensate spreads due to component variations. This paper addresses the implementation of these functions, introducing new circuit solutions. The quadrature voltage-controlled oscillator (VCO) relies on a ring of two tuned VCOs, where the oscillation frequency depends on inter-stage passive components only, demonstrating low noise and accurate quadrature phases. Prototypes, realized in 65-nm CMOS, show 56-60.4-GHz tunable oscillation frequency, phase noise better than 95 dBc/Hz at 1-MHz offset in the tuning range, 1.5 maximum phase error while consuming 22 mA from a 1-V supply. The frequency divider is based on clocked differential amplifiers, working as dynamic CML latches, achieving high speed and low power simultaneously. A divider by 4 realized in 65-nm CMOS occupies 15 m 30 m, features an operating frequency programmable from 20 to 70 GHz in nine bands and consumes 6.5 mW.

A Low Phase Noise, Wideband and Compact CMOS PLL for Use in a Heterodyne 802.15.3c Transceiver

Abstract: A low phase noise, wideband, mm-wave, integer-N PLL that is capable of supporting an 802.15.3c heterodyne transceiver is reported. The PLL can generate 6 equally spaced tones from 43.2 GHz to 51.84 GHz, which is suitable for a heterodyne architecture with FLO=(4/5)×FTRX. Phase noise is measured directly at the FLO frequency and is better than -97.5 dBc/Hz@1 MHz across the entire band. The reported frequency synthesizer is smaller, exhibits less phase noise, and consumes less power than prior art. In addition, the FLO tone corresponds to the fundamental of the VCO as opposed to a higher harmonic.

A TX VCO for WCDMA/EDGE in 90 nm RF CMOS

Abstract: A VCO is implemented in an RF 90 nm CMOS process and covers the frequency range 2.55-4.08 GHz. Drawing 19 mA from 1.2 V, the phase noise at 20 MHz frequency offset from a 3.7 GHz carrier is -156 dBc/Hz, meeting the phase noise requirement for GSM/EDGE and SAW-less WCDMA transmitter after frequency division by 2 or by 4. A second version of the VCO covers an additional 4.90-5.75 GHz range, at the expense of a higher phase noise in the added band. In this way, all currently operational WCDMA/EDGE bands can be synthesized by a single VCO working at the double or quadruple of the desired band.

A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation

Abstract: A highly linear calibration free VCO-based ADC uses a two-level modulator to eliminate distortion caused by tuning non-linearity of the VCO. The proposed architecture does not require a multi-level feedback DAC and eases anti-aliasing requirements. Fabricated in 90nm CMOS process, the prototype ADC achieves better than 71dB SFDR and 59.1dB SNDR in 8MHz signal bandwidth and consumes 4.3mW.

Non-linear optoelectronic phase-locked loop for stabilization of opto-millimeter waves: towards a narrow linewidth tunable THz source.

Abstract: We propose an optoelectronic phase-locked loop concept which enables to stabilize optical beat notes at high frequencies in the mm-wave domain. It relies on the use of a nonlinear-response Mach-Zehnder modulator. This concept is demonstrated at 100 GHz using a two-axis dual-frequency laser turned into a voltage controlled oscillator by means of an intracavity electrooptic crystal. A relative frequency stability better than 10⁻¹¹ is reported. This approach of optoelectronic down conversion opens the way to the realization of continuously tunable ultra-narrow linewidth THz radiation.

A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance

Abstract: Clock and data recovery (CDR) circuits with wide frequency acquisition range offer flexibility in optical communication networks, help reduce link power through activity-based rate adaptation, and minimize cost with a single-chip multi-standard solution. Extracting the bit rate from the incoming random data stream is the main challenge in implementing reference-less CDRs. A conventional rotational frequency detector has a limited acquisition range of about ±50% of the VCO frequency, consumes large power, and is susceptible to harmonic locking. Extending its range requires additional high-speed circuitry and a complex state machine [1]. The DLL-based architecture in [2] requires passing high-speed data through a long string of power-hungry buffers, imposes stringent matching requirements, and works only with ring oscillators. Other approaches require detailed statistical [3] or timing analysis [4]. Further, all the above techniques are only suitable for full-rate CDRs. In this paper, we present a reference-less half-rate CDR that uses a sub-harmonic extraction method to achieve unlimited frequency acquisition range. This technique is capable of locking the CDR to within 40ppm of any sub-rate of the data (making it applicable for any sub-rate CDR architecture), while being immune to undesirable harmonic locking. This CDR also integrates a calibration loop to improve robustness to input duty cycle error.

An injection-locked ring PLL with self-aligned injection window

Abstract: In modern analog front-ends, there is an increasing demand on high-performance analog-to-digital converters (ADCs), which require high sampling frequency and low-jitter sampling clock. This makes low-jitter phase-locked loops (PLLs) with jitter on the order of few picoseconds desirable. Unfortunately, due to stringent limit on die area, sometimes a PLL with a ring oscillator is the only choice. To get better phase noise, a wider loop bandwidth is needed to suppress the noise of the voltage-controlled oscillator (VCO). However, due to the discrete-time nature of the operations, the loop bandwidth is limited to one-tenth of the crystal oscillator (XTAL) frequency. One way to solve this problem is to use the injection-locking technique. This method exploits the clean reference clock but has several production problems. One is the frequency offset between injection signal and VCO, and this can be solved by using the injection-locked PLL architecture [1, 2]. However, in [1, 2] extra loops are still needed to adjust the injection window due to on-chip variations. In this work, an injection-locked ring PLL (ILRPLL) architecture is proposed to solve this problem. Using the concept of sub-sampling PLLs [3], the injection window is aligned automatically without feedback adjustment. A 432MHz ILRPLL is realized in ATV/DTV system to justify this technique.

A 60-GHz CMOS VCO Using Capacitance-Splitting and Gate–Drain Impedance-Balancing Techniques

Abstract: The design and measurement of a 60-GHz 90-nm CMOS voltage-controlled oscillator is presented. To reduce the power consumption and to improve the phase-noise performance, a capacitance-splitting and a gate-drain impedance-balancing techniques, which are realized with an inductive divider, are proposed. With these techniques, the size of the cross-coupled pair is reduced. Analysis of the proposed techniques shows that the transistor g m generation efficiency is improved and the oscillator noise factor is reduced. Moreover, the tank loaded quality factor is increased by balancing impedance levels across the transistor terminals. The 60-GHz oscillator was fabricated in a 90-nm CMOS technology. Under 0.6-V supply, the oscillator achieved a tuning range from 61.1 to 66.7 GHz, consuming only 3.16 mW. At 64 GHz, the phase noise is -95 dBc/Hz at 1-MHz offset.

High-swing class-C VCO

Abstract: By removing the tail current source of a class-C VCO, a high-swing VCO core has been introduced. The use of a transformer has added an additional degree of freedom so that a bias control circuit can adjust gate bias of the switching pair to a low voltage for the highest tank swing. High efficiency of class-C operation combined with high output swing led to a first class phase noise performance. The VCO oscillating at 5.11GHz, draws 1.44mA from a 0.6V power supply. The measured phase noise is −127dBc/Hz at 3MHz offset frequency resulting in a FoM of 192.3dB.

A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications

Abstract: In this paper, a low-cost, power efficient and fast Differential Cascode Voltage-Switch-Logic (DCVSL) based delay cell (named DCVSL-R) is proposed. We use the DCVSL-R cell to implement high frequency and power-critical delay cells and flip-flops of ring oscillators and frequency dividers. When compared to TSPC, DCVSL circuits offer small input and clock capacitance and a symmetric differential loading for previous RF stages. When compared to CML, they offer low transistor count, no headroom limitation, rail-to-rail swing and no static current consumption. However, DCVSL circuits suffer from a large low-to-high propagation delay, which limits their speed and results in asymmetrical output waveforms. The proposed DCVSL-R circuit embodies the benefits of DCVSL while reducing the total propagation delay, achieving faster operation. DCVSL-R also generates symmetrical output waveforms which are critical for differential circuits. Another contribution of this work is a closed-form delay model that predicts the speed of DCVSL circuits with 8% worst case accuracy. We implement two ring-oscillator-based VCOs in 0.13 μm technology with DCVSL and DCVSL-R delay cells. Measurements show that the proposed DCVSL-R based VCO consumes 30% less power than the DCVSL VCO for the same oscillation frequency (2.4 GHz) and same phase noise (-113 dBc/Hz at 10 MHz). DCVSL-R circuits are also used to implement the high frequency dual modulus prescaler (DMP) of a 2.4 GHz frequency synthesizer in 0.18 μm technology. The DMP consumes only 0.8 mW at 2.48 GHz, a 40% reduction in power when compared to other reported DMPs with similar division ratios and operating frequencies. The RF buffer that drives the DMP consumes only 0.27 mW, demonstrating the lowest combined DMP and buffer power consumption among similar synthesizers in literature.

Analysis of a neural oscillator

Abstract: Although the Matsuoka neural oscillator, which was originally proposed as a model of central pattern generators, has widely been used for various robots performing rhythmic movements, its characteristics are not clearly explained even now. This article shows two closed-form relations that express the frequency and amplitude of the generated oscillation as functions of the parameters of the model. Although they are derived based on a rough linear approximation, they accord with the result obtained by a simulation considerably. The obtained relations also give us some nontrivial predictions about the properties of the oscillator.

Determination of Sweep Linearity Requirements in FMCW Radar Systems Based on Simple Voltage-Controlled Oscillator Sources

Abstract: Linear frequency modulated (FM), or chirp, pulse compression is a widely used technique for improving the range resolution of radar systems, although it often places quite stringent demands on FM sweep linearity. This paper examines the impact of sweep nonlinearities on the performance of frequency modulated continuous wave (FMCW) radar systems, particularly those employing simple voltage-controlled oscillator (VCO) sources, using a new and straightforward approach based on the fractional slope variation (FSV). Modeled results are presented, assuming a square-law source nonlinearity representation, showing the effect of such nonlinearities on point-target response and range resolution. These results are then related to the standard definition of linearity. Measurements from a commercial VCO are finally used to convincingly validate the work, resulting in a simple and practical method to predict the impact of source nonlinearity, as defined by the FSV parameter, on the performance of an FMCW radar system.

A 250 mV, 352 $\mu$ W GPS Receiver RF Front-End in 130 nm CMOS

Abstract: A fully integrated CMOS GPS receiver RF front-end is presented. Systematic circuit optimizations for ultra-low voltage operation including subthreshold biasing, a novel mixer-VCO interface, and charge neutralization enable the supply voltage to be dramatically reduced as a means to save power. The 250 mV supply is the lowest ever reported for any integrated receiver RF front-end to date. Its 352 μW power consumption represents a three times power savings compared to the prior lowest GPS receiver RF front-ends reported in the literature. The prototype was fabricated in a 1P8M 130 nm CMOS process and includes a variable gain LNA, a quadrature VCO, quadrature mixers, and all required bias circuitry. The system has a measured gain of 42 dB, a noise figure of 7.2 dB, and an oscillator phase noise of - 112.4 dBc/Hz at a 1 MHz offset, resulting in a VCO FoM of 187.4 dBc/Hz.

Memristor-based reactance-less oscillator

Abstract: The first reactance-less oscillator is introduced. By using a memristor, the oscillator can be fully implemented on-chip without the need for any capacitors or inductors, which results in an area-efficient fully integrated solution. The concept of operation of the proposed oscillator is explained and detailed mathematical analysis is introduced. Closed-form expressions for the oscillation frequency and oscillation conditions are derived. Finally, the derived equations are verified with circuit simulations showing excellent agreement.

A Novel Variable Inductor Using a Bridge Circuit and Its Application to a 5–20 GHz Tunable LC-VCO

Abstract: A novel variable inductor using a bridge circuit is proposed. Because of a bypass switch MOSFET placed at a balance point, the effect of the switch resistance which is a penalty of the variable inductance is suppressed and degradation of the Q factor is mitigated. A 10-20 GHz tunable LC-VCO core using this inductor was also fabricated. Because of the multi-stage variable inductor, 20 GHz operation having over 10 GHz continuous tuning range with phase noise of -103 to -84 dBc/Hz is achieved with only 5.2 to 7.1 mW power consumption. By using a 1/2 divider, a 5-20 GHz continuous tuning range is also obtained. The chip area is 1/10 smaller than that of conventional wide range LC-VCOs because of the miniature 3-D structure variable inductor. This variable inductor and the wide range LC-VCO are suit able for the clock generation of high-speed communication systems, multi-core processors, as well as low-power, low-cost wireless transceivers.

LC-VCO Design Optimization Methodology Based on the $g_m/I_D$ Ratio for Nanometer CMOS Technologies

Abstract: In this paper, an LC voltage-controlled oscillator (LC VCO) design optimization methodology based on the gm/ID tech nique and on the exploration of all inversion regions of the MOS transistor (MOST) is presented. An in-depth study of the com promises between phase noise and current consumption permits optimization of the design for given specifications. Semiempirical models of MOSTs and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design tradeoffs are easily identified. Four LC-VCO designs in different inversion regions in a 90-nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4-GHz VCO operating in moderate inversion. The designed VCO draws 440 μA from a 1.2-V power supply and presents a phase noise of -106.2 dBc/Hz at 400 kHz from the carrier.

A Low Power, Startup Ensured and Constant Amplitude Class-C VCO in 0.18 $\mu {\rm m}$ CMOS

Abstract: A low power and robust class-C voltage-controlled oscillator (VCO) is presented in this letter. It features 1) an automatic startup loop to achieve the optimal point and address the inherent risk of startup failure and 2) a digital amplitude control loop to stabilize amplitude and enhance the PVT (process, voltage and temperature) tolerance. The design is implemented in a 0.18 μm CMOS process. Measurement demonstrates the VCO has a 20% tuning range and phase noise of -123.0 dBc/Hz at 1 MHz offset from a 3.1 GHz carrier while consuming 1.57-mW power from a 1 V supply, yielding a Figure-of-Merit (FoM) of 191.1. While operating under the minimum power of 560 μW, it produces -111.3 dBc/Hz phase noise at 1 MHz offset from a 3.1 GHz carrier showing a 183.8 FoM.

A 475 mV, 4.9 GHz Enhanced Swing Differential Colpitts VCO With Phase Noise of -136 dBc/Hz at a 3 MHz Offset Frequency

Abstract: A new enhanced swing differential Colpitts VCO architecture enables oscillations to go beyond both the supply voltage and ground making it suitable for low voltage operation. Analysis for the oscillation frequency, differential- and common-mode oscillations, amplitude of oscillation, and start-up condition provides insight into oscillator operation and design considerations. Operating at 4.9 GHz, the VCO consumes from 1.9 mW to 3 mW for supply voltages of 400 mV and 500 mV, respectively. The 130 nm CMOS VCO's measured phase noise ranges from -132.6 to -136.2 dBc/Hz at a 3 MHz offset frequency.

A 4.6GHz MDLL with −46dBc reference spur and aperture position tuning

Abstract: Multiplying delay-locked loops (MDLLs) [1–5] have been shown to have improved jitter accumulation and tracking over VCO-based PLLs. By injecting the reference clock edge into the VCO at each reference cycle, an MDLL removes the accumulated jitter of the VCO. The principal challenge in MDLL design is to align the injected reference edge with the loop feedback signal. Timing mismatch between the reference edge and the VCO feedback edge, or offsets in the charge pump, would introduce a phase error in the injected edge. The error manifests as a period jitter or reference spur in the frequency domain. This effect limits the minimum jitter attained by the MDLL.

A mm-Wave quadrature VCO based on magnetically coupled resonators

Abstract: Wireless signal processing at mm-Waves would benefit from the availability of a quadrature signal reference, enabling direct-conversion transceiver architectures and providing phase rotators drivers in phased arrays systems [1]. They are furthermore attractive for clock recovery in ICs for wireline applications. Search of a compact quadrature generator at around 60GHz with low phase noise at moderate power is the topic of this work. Discarding a double-frequency VCO followed by dividers-by-two given the high frequency range of operation, the most suitable topology borrowed by RF solutions is represented by cross-coupled LC voltage-controlled oscillators [2]. However, the oscillation frequency dependence on the biasing current makes it susceptible to phase noise, close-in in particular [3]. At mm-Waves, this is exacerbated by core devices of small dimensions to such an extent that 1/f3 noise remains dominant up to more than ∼10MHz, making it unsuitable for stringent applications. On the contrary a ring of two VCOs magnetically coupled to each other, as shown in Fig. 16.2.1, has an oscillation frequency dependence on inter-stage passive components only, low 1/f3 noise together with good quadrature accuracy. The quadrature oscillator has been realized in a 65nm CMOS technology and prototypes show the following performances: 56-to-60.3GHz tunable oscillation frequency, phase noise better than −95dBc/Hz at 1MHz offset in the tuning range, 1.5° maximum phase error while consuming 22mA from a 1V supply.

An Active Inductor-Based VCO With Wide Tuning Range and High DC-to-RF Power Efficiency

Abstract: An active inductor-based voltage-controlled oscillator (VCO) with a wide frequency tuning range was designed and fabricated using a standard 0.13-μm CMOS process. The oscillator has an LC-tank topology with cross-coupled transistors, and the active inductor was realized using a pair of fully differential very high-speed operational transconductance amplifiers. Due to the differential nature of the inductor, the even harmonics of the output signal were much reduced. Measured results show that the VCO is tunable from 833 MHz to 3.72 GHz, representing a tuning range of 127%. The VCO can produce -0.9 dBm of radio-frequency power. The core circuit, excluding output buffers, consumes 13 mW from a 1.2-V supply.

Design of a Dual W- and D-Band PLL

Abstract: This paper describes the design considerations and performance of the highest frequency phase-locked loop (PLL) reported to date. The PLL was fabricated in a 0.13-μm SiGe BiCMOS process and integrates on a single die: a fundamental-frequency 86-92 GHz Colpitts voltage-controlled oscillator (VCO), a differential push-push 160-GHz Colpitts VCO with two differential outputs at 80 GHz, a programmable divider chain, the charge pump, and all loop filter components. It achieves the lowest W- and D-band phase noise of -93 dBc/Hz at 90 GHz and -87.5 dBc/Hz at 163 GHz, both measured at a 100 kHz offset, and demonstrates an extended locking range of 80-100 GHz at the fundamental frequency, and 160-169 GHz at the second harmonic output of the push-push VCO. The single-ended PLL output power is -3 dBm at 90 GHz and -25 dBm at 164 GHz. The chip consumes 1.25 W from 1.8 V, 2.5 V, and 3.3 V supplies and occupies 1.1 mm × 1.7 mm, including pads.

A 0.5-V, 440-µW frequency synthesizer for implantable medical devices

Abstract: This paper presents an ultra-low-power, low-voltage frequency synthesizer designed for medical implantable devices. Several design techniques are adopted to address the issues in ultra-low voltage design. The charge pump (CP) in the synthesizer utilizes dynamic threshold-voltage and switch-coupled techniques to provide a high driving current while maintaining a low standby current. The synthesizer adopts a ring-based voltage-controlled oscillator (VCO) that utilizes a dual resistor-varactor tuning technique for compensating process-voltage-temperature (PVT) variations and the exponential voltage-to-current curve. Implemented in a 130-nm CMOS technology, the 0.5-V medical-band frequency synthesizer consumes 440 µW with a phase noise of −91.5 dBc/Hz at 1-MHz frequency offset.

A Low-Power GSM/EDGE/WCDMA Polar Transmitter in 65-nm CMOS

Abstract: A low-power, multimode polar transmitter based on a two-point injection PLL with a linearized VCO is implemented in 65-nm CMOS technology. A wideband feedback loop, nested inside the PLL with negligible area and power consumption overhead, linearizes and accurately controls the tuning characteristic of the VCO, which is a key requirement when directly modulating the oscillator. Differential delay between AM-PM paths is predictable and is self-calibrated. In WCDMA mode, the transmitter achieves 42/-58-dBc ACLR at 5/10-MHz offsets, -159-dBc/Hz receive band noise, and 2.9% EVM at 0-dBm output power while drawing 40-mA from a 3.6-V battery. The DG09 battery current is 25-mA based on a typical PA gain profile and the chip active area is 0.7-mm2.