Showing papers on "Voltage-controlled oscillator published in 2012"

A Low-Phase-Noise Wide-Tuning-Range Oscillator Based on Resonant Mode Switching

Abstract: In this paper we will present a low-phase-noise wide-tuning-range oscillator suitable for scaled CMOS processes. It switches between the two resonant modes of a high-order LC resonator that consists of two identical LC tanks coupled by capacitor and transformer. The mode switching method does not add lossy switches to the resonator and thus doubles frequency tuning range without degrading phase noise performance. Moreover, the coupled resonator leads to 3 dB lower phase noise than a single LC tank, which provides a way of achieving low phase noise in scaled CMOS process. Finally, the novel way of using inductive and capacitive coupling jointly decouples frequency separation and tank impedances of the two resonant modes, and makes it possible to achieve balanced performance. The proposed structure is verified by a prototype in a low power 65 nm CMOS process, which covers all cellular bands with a continuous tuning range of 2.5-5.6 GHz and meets all stringent phase noise specifications of cellular standards. It uses a 0.6 V power supply and achieves excellent phase noise figure-of-merit (FoM) of 192.5 dB at 3.7 GHz and >; 188 dB across the entire tuning range. This demonstrates the possibility of achieving low phase noise and wide tuning range at the same time in scaled CMOS processes.

A Fundamental Frequency 120-GHz SiGe BiCMOS Distance Sensor With Integrated Antenna

Abstract: This paper describes the first fundamental frequency single-chip transceiver operating at -band. The low-IF monostatic transceiver integrates on a single chip two 120-GHz voltage-controlled oscillators (VCOs), a 120-GHz divide-by-64 chain, two in-phase/quadrature (IQ) receivers with phase-calibration circuitry, a variable gain transmit amplifier, an antenna directional coupler, a patch antenna, bias circuitry, a transmit power detector, and a temperature sensor. A quartz antenna resonator with 6-dBi gain and simulated 50% efficiency is placed directly above the on-chip patch to transmit and receive the 120-GHz signals. The circuit with the above-integrated-circuit antenna occupies an area of 2.2 mm 2.6 mm, consumes 900 mW from 1.2- and 1.8-V supplies, and was wire-bonded in an open-lid 7 mm 7 mm quad-flat no-leads package. Some transceiver performance parameters were characterized on the packaged chip, mounted on an evaluation board, while others, such as receiver noise figure and VCO phase noise at the 120-GHz output were measured on circuit breakouts. The AMOS-varactor VCOs have a typical phase noise of at 1-MHz offset and a tuning range of 115.2-123.9 GHz. The receiver gain and the transmitter output power are each adjustable over a range of 15 dB with a maximum transmitter output power of 3.6 dBm. The receiver IQ phase difference, measured at the IF outputs of the packaged transceiver, is adjustable from 70° to 110°, while the amplitude imbalance remains less than 1 dB. The receiver breakout gain and double-sideband noise figure are 10.5-13 and 10.5-11.5 dB, respectively, with an input compression point of . Several experiments were conducted through the air over distances of up to 2.1 m with a focusing lens placed above the packaged chip.

A 16-mW 78-dB SNDR 10-MHz BW CT $\Delta \Sigma$ ADC Using Residue-Cancelling VCO-Based Quantizer

Abstract: This paper presents a continuous-time (CT) ΔΣ modulator using a VCO-based internal quantizer. It incorporates a nonlinear VCO as the second stage in a two-stage residue canceling quantizer (RCQ) and mitigates the impact of its nonlinearity by spanning only a small region of the VCO's V-to-F nonlinear tuning curve. The order of noise shaping is increased by placing the RCQ in a continuous-time ΔΣ loop. Using only a first order loop filter, the proposed ΔΣ modulator achieves second order noise shaping. Fabricated in a 90-nm CMOS process, the prototype modulator occupies an active area of 0.36 mm2 and consumes 16 mW power. It achieves a peak SNDR of 78.3 dB in 10-MHz bandwidth and an SFDR of better than 85 dB when clocked at 600 MHz. The figure of merit of the modulator is 120 fJ/conv-step.

A Novel CMOS High-Power Terahertz VCO Based on Coupled Oscillators: Theory and Implementation

Abstract: We introduce a novel frequency tuning method for high-power terahertz sources in CMOS. In this technique, multiple core oscillators are coupled to generate, combine, and deliver their harmonic power to the output node without using varactors. By exploiting the theory of nonlinear dynamics, we control the coupling between the cores to set their phase shift and frequency. Using this method, two high-power terahertz VCOs are fabricated in a 65 nm LP bulk CMOS process. The first one has a measured output power of 0.76 mW at 290 GHz with 4.5% tuning range and the output power of the second VCO is 0.46 mW at 320 GHz with 2.6% tuning range. The output power of these signal sources is 4 orders of magnitude higher than previous CMOS VCOs and is even higher than VCOs implemented in compound semiconductors with much higher cut-off frequencies.

A Self-Sustained CMOS Microwave Chemical Sensor Using a Frequency Synthesizer

Abstract: In this paper, a CMOS on-chip sensor is presented to detect dielectric constant of organic chemicals. The dielectric constant of these chemicals is measured using the oscillation frequency shift of an LC voltage-controlled oscillator (VCO) upon the change of the tank capacitance when exposed to the liquid. To make the system self-sustained, the VCO is embedded inside a frequency synthesizer to convert the frequency shift into voltage that can be digitized using an on-chip analog-to-digital converter. The dielectric constant is then estimated using a detection procedure including the calibration of the sensor. The dielectric constants of different organic liquids have been detected in the frequency range of 7-9 GHz with an accuracy of 3.7% compared with theoretical values for sample volumes of 10-20 μL. The sensor is also applicable for binary mixture detection and estimation of the fractional volume of the constituting materials with an accuracy of 1%-2%.

A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With −36 dB EVM at 5 mW Power

Abstract: Polar or outphasing radio transmitter architectures promise higher efficiency than their Cartesian counterparts [1], but require the adoption of phase modulators with bandwidth about one order of magnitude wider than the channel bandwidth. In contrast to phase-switching approaches [2], efficient implementations of wideband phase modulators are based on the direct frequency modulation (FM) of a PLL and on the two-point signal-injection scheme [3]. Unfortunately, meeting the noise/bandwidth requirements of 4G wireless standards (such as WiMAX) demands fine frequency resolution, tight VCO linearity and accurate synchronization between the two signals injected into the PLL. This paper introduces a digital-intensive phase modulator circuit, which is able to enforce an arbitrary carrier phase change (up to ±π radians) in one clock sample. For a clock frequency of 40MHz, the modulation error, expressed in terms of error vector magnitude (EVM), is below −36dB for a 20Mb/s QPSK-modulated or a 10Mb/s GMSK-modulated carrier at 3.6GHz.

A 1.9–3.8 GHz $\Delta \Sigma$ Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency

Abstract: A fast and high-precision all-digital automatic calibration circuit that is highly suited for ΔΣ fractional-N synthesizers is designed to achieve a constant loop bandwidth and fast lock time over an octave tuning range. A high-speed frequency-to-digital converter (FDC) measures VCO frequency on-chip with a sub-fREF frequency resolution of fREF/k in a time period of k·TREF. The on-chip detected VCO frequency is then used for calibrating the loop bandwidth and the VCO frequency. The loop bandwidth calibration circuit measures the VCO gain KVCO and uses it to precisely control the charge pump current, hence making the loop bandwidth constant. For the VCO frequency calibration, a minimum error code finding block significantly enhances the calibration accuracy by finding the truly closest code to the target frequency. Moreover, this method does not need to activate ΔΣ modulator to achieve sub- fREF calibration resolution, which makes this technique much accurate and faster than the conventional ones. A 1.9-3.8 GHz ΔΣ fractional-N synthesizer is implemented in 0.13 μm CMOS, demonstrating that the loop bandwidth calibration is completed in 1.1-6.0 μs with ±2% accuracy and the VCO frequency calibration is completed in 1.225-4.025 μs, all across the entire octave tuning range.

A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing

Abstract: A low-phase-noise integer-N phase-locked loop (PLL) is attractive in many applications, such as clock generation and analog-to-digital conversion. The sub-harmonically injection-locked technique [1–3], sub-sampling technique [4], and the multiplying delay-locked loop (MDLL) [5–8] can significantly improve the phase noise of an integer-N PLL. In the sub-harmonically injection-locked technique, to inject a low-frequency reference clock into a high-frequency voltage-controlled oscillator (VCO), the injection timing should be tightly controlled [2–3]. If the injection timing varies due to process variation, it may cause a large reference spur or even cause the PLL to fails to lock [3]. In [1], a sub-harmonically injection-locked PLL (SILPLL) adopts a sub-sampling phase-detector (PD) [4] to automatically align the phase between the injection pulse and a VCO. However, a sub-sampling PD has a small capture range and a low bandwidth. The high-frequency non-linear effects of a sub-sampling PD may degrade the accuracy and limit the maximum speed of a VCO. In addition, a frequency-locked loop is needed for a sub-sampling PD. In [3], a delay line is manually adjusted to achieve the correct injection timing. However, the delay line is sensitive to process variations. Thus, the injection timing should be calibrated.

A 283-to-296GHz VCO with 0.76mW peak output power in 65nm CMOS

Abstract: Sub-mm-Wave and terahertz frequencies have many applications such as medical imaging, spectroscopy and communication systems. CMOS signal generation at this frequency range is a major challenge due to the limited cut-off frequency of transistors and their low breakdown voltage. A recent work has demonstrated generation of high power at a fixed frequency in the sub-mm-Wave range using a harmonic oscillator [1]. However, for most applications a tunable signal source is necessary. In previous works, frequency multipliers are used as an alternative for tunable power generation above 150GHz [2]. In this work, for the first time we introduce a tunable high-power oscillator at sub-mm-Wave frequencies in low-power (LP) bulk CMOS.

Analysis and Design of Transformer-Based Dual-Band VCO for Software-Defined Radios

Abstract: This work presents complete analysis of both one- port and two-port dual-band oscillators using transformer-based fourth-order LC tanks, from which critical parameters including oscillation frequency, start-up condition, tank Q, phase noise-are thoroughly derived and compared. It is shown that one-port oscillators consume less power than two-port counterparts but may suffer from stability problem which can be solved by a notch-peak cancellation technique. On the other hand, compared to one-port oscillators, two-port oscillators need to consume more power to obtain the same output swing, but their phase noise can be improved more linearly with increasing bias current, and thus they can achieve lower phase noise with a sufficiently large bias current. Based on the results, a dual-band quadrature voltage- controlled oscillator (Q-VCO) is systematically designed and implemented in a 0.13- m CMOS process for software-defined -radio (SDR) applications, in which the two-port topology is used in the low band for low phase noise and the one-port topology is employed in the high band for low power consumption. The prototype achieves a dual-band operation with in-phase and quadrature-phase (IQ) output signals from 2.7 GHz to 4.3 GHz and from 8.4 GHz to 12.4 GHz. At 3.6 GHz and 10.4 GHz, phase noise at 3 MHz offset of dBc/Hz and dBc/Hz and sideband-rejection ratios (SBR) of 37 dB and 41 dB are measured, respectively.

Design of Low Phase-Noise Microwave Oscillator and Wideband VCO Based on Microstrip Combline Bandpass Filters

Abstract: This paper presents a new low phase-noise microwave oscillator and wideband voltage-controlled oscillator (VCO) based on microstrip combline bandpass filters. For this type of oscillator, the passband filter is embedded into the feedback loop to treat as a frequency stabilization element. Instead of designing the oscillator at the group-delay-peak frequency of the filter to achieve a good phase-noise performance, in this paper, the peak frequency of the complex quality factor Qsc is adopted for oscillator design. To demonstrate the effectiveness of using Qsc-peak frequency, two filter-based oscillators are implemented at the Qsc-peak and group-delay-peak frequencies, respectively. The oscillator designed at the Qsc-peak frequency improves the phase-noise about 10 dB as compared with that realized at the group-delay-peak frequency. The developed oscillator with the three-pole combline filter is experimentally demonstrated at 2.05 GHz with -148.3-dBc/Hz phase noise at 1-MHz offset frequency. Moreover, by attaching a varactor on each resonator of the combline filter, the oscillator can be extended to a wideband VCO. The developed VCO has a frequency tuning range from 1.3 to 2.2813 GHz with a 54.8% bandwidth. Over this frequency range, all the phase noises measured at 1-MHz offset frequency are better than -117.19 dBc/Hz.

$K$ -Band CMOS Differential and Quadrature Voltage-Controlled Oscillators for Low Phase-Noise and Low-Power Applications

Abstract: In this paper, modified circuit topologies of a differential voltage-controlled oscillator (VCO) and a quadrature VCO (QVCO) in a standard bulk 90-nm CMOS process are presented for low dc power and low phase-noise applications. By utilizing current-reuse and transformer-feedback techniques, the proposed VCO and QVCO can be operated at reduced dc power consumption while maintaining extraordinary circuit performance in terms of low phase-noise and low amplitude/phase errors. The VCO circuit topology is investigated to obtain the design procedure. The VCO is further applied to the QVCO design with a bottom-series coupling technique. The coupling network between two differential VCOs and device size are properly designed based on our proposed design methodology to achieve low amplitude and phase errors. Moreover, the VCO and the QVCO are fully characterized with amplitude and phase errors via a four-port vector network analyzer. With a dc power of 3 mW, the VCO exhibits a frequency tuning range from 20.3 to 21.3 GHz, a phase noise of - 116.4 dBc/Hz at 1-MHz offset, a figure-of-merit (FOM) of -198 dBc/Hz, a phase error of 3.8° , and an amplitude error of 0.9 dB. With a dc power of 6 mW, the QVCO demonstrates a phase noise of -117.4 dBc/Hz, a FOM of -195.6 dBc/Hz, a phase error of 4° , and an amplitude error of 0.6 dB. The proposed VCO and QVCO can be compared with the previously reported state-of-the-art VCOs and QVCOs in silicon-based technologies.

An Ultra Low-Power CMOS Transceiver Using Various Low-Power Techniques for LR-WPAN Applications

Abstract: In this work, we implemented and evaluated a fully integrated 2.4 GHz CMOS RF transceiver using various low-power techniques for low-rate wireless personal area network (IEEE 802.15.4 LR_WPAN) applications in 0.18-μm CMOS technology. In order to achieve an ultra low power consumption, a RC oscillator (OSC) operating below 200 nA, a regulator operating below 200 nA for sleep mode, a quick start block for the crystal oscillator, a passive wake-up circuit, a LNA with negative gm, a current bleeding mixer, and a stacked VCO are all implemented in this transceiver. The transmitter achieves less than 5.0% error vector magnitude (EVM) at 5 dBm output, and the receiver sensitivity is -101 dBm. The sensitivity of the wake-up block is -29.8 dBm. The current consumption is below 14.3 mA for the data receiving mode, 16.7 mA for the transmitter, and less than 600 nA for the sleep mode from a 1.8 V power supply. That is considered to be lowest for the 2.4 GHz CMOS ZigBee transceiver compared to open literature results.

A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer

Abstract: Voltage-controlled oscillator (VCO) based analog-to-digital conversion presents an attractive means of implementing high-bandwidth oversampling ADCs [1,2]. They exhibit inherent noise-shaping properties and can operate at low supply voltages and high sampling rates [1–3]. However, usage of VCO-based ADCs has been limited due to their nonlinear voltage-to-frequency (V-to-F) transfer characteristic, which severely degrades their distortion performance. Digital calibration is used to combat nonlinearity in an open-loop VCO-based ADC, but 1st-order noise-shaping mandates high OSRs, thus increasing power dissipation in digital circuits, even in a nanometer-scale CMOS process [1]. In [2], nonlinearity is suppressed by embedding the VCO in a ΔΣ loop. While this technique works in principle, the need for large loop gain at high frequencies makes it very difficult to achieve high SNDR. For instance, the suppression level near the band edge is approximately 20dB for a VCO-based 2nd-order modulator operating with an over-sampling ratio (OSR) of 30. Our ADC overcomes the impact of VCO non-linearity by minimizing the input signal processed by the VCO. The prototype achieves 78.3dB SNDR in a 10MHz signal bandwidth at 600MHz sampling rate, while consuming 16mW power.

Resistor-less current-mode four-phase quadrature oscillator using CCCDTAs and grounded capacitors

Abstract: A current-mode four-phase quadrature oscillator (FPQO) using 2 current controlled current differencing transconductance amplifiers (CCCDTAs) and 2 grounded capacitors is presented. The proposed oscillator can provide 4 sinusoidal output currents with 90 phase difference. The oscillation condition and oscillation frequency can be controlled independently and electronically by adjusting the bias currents of the CCCDTA. Both the oscillation condition and oscillation frequency tuning laws are non-interactive and dual-current controlled. High output impedances of the configuration enable the circuit to be cascaded without additional current buffers. The use of only grounded capacitors is ideal for integration. The circuit performances are depicted through PSPICE simulations, they show good agreement to theoretical anticipation.

Optically Tunable Frequency-Doubling Brillouin Optoelectronic Oscillator With Carrier Phase-Shifted Double Sideband Modulation

Abstract: An optically tunable frequency-doubling optoelectronic oscillator (FD-OEO) based on stimulated Brillouin scattering (SBS) and carrier phase-shifted double sideband (CPS-DSB) modulation is proposed and demonstrated. SBS effect provides narrowband filtering for the OEO to generate an oscillation signal with frequency equal to the Brillouin frequency shift, while a CPS-DSB modulation by using a dual-parallel Mach-Zehnder modulator is implemented to double the oscillation frequency. Owing to the wavelength-dependent Brillouin frequency shift, frequency tunability is realized by tuning the wavelength of the laser source. In the experiments, frequency-doubling microwave signals from 18.38 to 18.74 GHz are generated when the wavelength of the laser source is tuned from 1565 to 1535 nm.

A Self-Sustained Microwave System for Dielectric-Constant Measurement of Lossy Organic Liquids

Abstract: In this paper, dielectric constants of lossy organic liquids are measured using oscillation frequency shifts of a negative-resistance voltage-controlled oscillator (VCO). The design and working principle of the oscillator and the effect of material loss are presented in detail. The proposed method provides relatively large frequency shifts of 10-110 MHz for lossy test sample volumes of 50-200 μL whose dielectric constants are between 2-13 at 4.5 GHz, thereby allowing good resolution in dielectric-constant measurement. To make the system self-sustained, the VCO is used as part of a frequency synthesizer system for frequency-to-voltage conversion and digital extraction of the frequency shift using a unique detection algorithm. The dielectric constant of several organic liquids have been extracted to an accuracy better than 2% using sample volumes of 50-200 μL , and has excellent agreement with reported values. The applicability of this system for sensing dielectric mixtures has also been shown, and volume fraction estimation has been demonstrated to an accuracy of around 1%.

A 6.7-to-9.2GHz 55nm CMOS hybrid Class-B/Class-C cellular TX VCO

Abstract: The design of very-wide-band CMOS voltage-controlled oscillators (VCOs) compliant with the phase-noise specifications of cellular transmitters is non-trivial, especially considering the GSM standard, where the phase noise exhibited by the local oscillator (LO, generated by the cascade of VCO, buffers, and usually frequency dividers) should be several dB below −162dBc/Hz at 20MHz frequency offset from the carrier. As shown in [1], challenging phase-noise requirements can embrace the WCDMA transmitter as well (e.g. −166dBc/Hz at 45MHz frequency offset for WCDMA band VIII), if cheap antenna duplexers are chosen to minimize costs. In such scenarios, and particularly in the very relevant case of WCDMA transmitting at moderate power levels, the LO power efficiency is still one of the limiting factors for a long-lasting battery life, motivating the ongoing quest for VCO power optimization.

A 0.5-V, 440-µW Frequency Synthesizer for Implantable Medical Devices

Abstract: An ultra-low-power, low-voltage frequency synthesizer designed for implantable medical devices is presented. Several design techniques are adopted to address the issues in ultra-low voltage and current design. The charge pump (CP) in the synthesizer utilizes dynamic threshold-voltage and switch-coupled techniques to provide a high driving current with a low standby current. The synthesizer adopts a ring-based voltage controlled oscillator (VCO) that utilizes a dual resistor-varactor tuning technique to compensate for process-voltage-temperature (PVT) variations and the exponential voltage-to-current curve. Implemented in a 0.13-μm CMOS technology, the 0.5-V medical-band frequency synthesizer consumes 440 μW while exhibiting a phase noise of 91.5 dBc/Hz at 1-MHz frequency offset.

A 245 GHz transmitter in SiGe technology

Abstract: A 245 GHz transmitter for sensing applications has been realized, which consists of a push-push VCO with 1/64 frequency divider, a transformer- coupled one-stage power amplifier, and a frequency doubler. It is fabricated in 0.13µm SiGe:C BiCMOS technology with f T /f max of 300GHz/500GHz. The peak output power of the transmitter is 2 dBm. The 3-dB bandwidth reaches from 229 GHz to 251 GHz. The output power is 1 dBm at 245 GHz. The transmitter dissipates 0.29 W. Additionally, a test-circuit with an integrated two-stage power amplifier and a frequency doubler is presented, which reaches 1.4 dBm at 245 GHz and dissipates 0.19 W.

Ring oscillator delta sigma adc modulator with replica path nonlinearity calibration

Abstract: An embodiment provides a continuous-time delta-sigma modulator for analog-to-digital conversion. The modulator includes a signal path generating including a ring voltage controlled oscillator driven by an analog input signal. The signal path produces digital values by sampling the ring voltage controlled oscillator. A calibration circuit measures nonlinear distortion coefficients in a replica of the signal path. A nonlinearity corrector corrects the digital values based upon determined nonlinear distortion coefficients. Preferred embodiment ADC ΔΣ modulators do not require any analog integrators, feedback DACs, comparators, or reference voltages, and do not require a low jitter clock.

13 GHz CMOS Active Inductor LC VCO

Abstract: A 13 GHz active inductor LC voltage controlled oscillator (VCO) has been realized in 90 nm CMOS technology by ST-Microelectronics. The VCO consists of two complementary cross-coupled pairs, an active LC tank implemented by means of a differential high-Q low-noise active inductor and two p-MOSFET varicaps, and an output buffer stage. The measurements show a phase noise of -105.25 dBc/Hz at 1 MHz frequency offset. The current consumption of the VCO core and differential boot-strapped inductor amount to 0.7 and 1.8 mA, respectively, from a 1.2 V supply voltage.

Integration of Current-Reused VCO and Frequency Tripler for 24-GHz Low-Power Phase-Locked Loop Applications

Abstract: This brief presents the integration of an 8-GHz voltage-controlled oscillator (VCO) and a frequency tripler for 24-GHz local oscillator generation. By stacking the VCO and the tripler with a current-reused topology, the power consumption of this integration can be saved. The proposed circuit with a total chip area of 0.7 mm × 0.8 mm is implemented in a 0.18-μm CMOS process. As the tuning voltage increases from 0 to 2 V, the measured frequency tuning range (FTR) of the VCO is from 7.06 to 8.33 GHz. The final resulting output frequency from the tripler ranges from 21.18 to 24.98 GHz (16.5% FTR). The core circuit totally consumes 5 mA from a 1.8-V supply voltage. The measured phase noises at the VCO and frequency tripler outputs are -113.76 and -105.1 dBc/Hz at 1-MHz offset frequency, respectively, when Vtune is 0 V. The best evaluated figure of merit with tuning is -187.2 dBc/Hz. This integration of a VCO and a frequency tripler exhibits a high potential for the use in low-power 24-GHz phase-locked loops.

A wideband fractional-N PLL with suppressed charge-pump noise and automatic loop filter calibration

Abstract: This paper explores a new topology of charge-pump PLL intended for ΔΣ-fractional-N frequency synthesis. Thanks to the adoption of a bang-bang phase detector and a two-path analog loop filter, the impact of charge-pump noise on PLL phase noise is reduced to negligible levels with no penalty on power dissipation. Additionally, the proposed topology enables an efficient cancellation of the ΔΣ quantization error, a novel scheme for the calibration of the loop filter parameters and a low-sensitivity VCO, which is beneficial in lowering the reference-spur level. The 3.0-to-4.0-GHz fractional-N synthesizer integrated in a 65-nm CMOS technology consumes 5 mW from a 1.2-V voltage supply. The flat phase noise is -105 dBc/Hz over the 5.5-MHz PLL bandwidth with a 40-MHz crystal reference.

A new single MCCCDTA based Wien-bridge oscillator with AGC

Abstract: This paper presents a new current-mode Wien-bridge oscillator with automatic amplitude control. The oscillator only employs single MCCCDTA as the active element and provides two current outputs with small distortion from high output impedances. Its oscillation condition and frequency can be tuned electronically, linearly and independently through tuning bias currents of MCCCDTA. The circuit simulation results are in agreement with theory.

Flicker Noise Up-Conversion due to Harmonic Distortion in Van der Pol CMOS Oscillators

Abstract: Harmonic content modulation of the oscillator output voltage can contribute to flicker noise up-conversion in LC-tuned oscillators. The paper reports a quantitative analysis of the effect in Van der Pol oscillators using the framework of the impulse sensitivity function (ISF). It is shown that most of the up-conversion efficiency results from the first harmonic of the ISF, which is not perfectly in quadrature to the output voltage waveform, and from the first harmonic of the transistor current, which is slightly lagging the voltage waveform. A closed-form expression of 1/f3 phase noise in voltage-limited LC-tuned oscillator is derived that is in good agreement with circuit simulations. The paper also shows that the values of both phase shifts are determined by the non-linearity of the active element and are linked to the relevant oscillator parameters, i.e., excess gain and tank quality factor.

A 0.6-V Quadrature VCO With Enhanced Swing and Optimized Capacitive Coupling for Phase Noise Reduction

Abstract: This paper presents a 0.6-V quadrature voltage-controlled oscillator (QVCO) with enhanced swing for low power supply applications. The QVCO comprises a novel capacitive coupling technique that is employed not only for quadrature signal coupling, but also for phase noise reduction. As a result, the proposed QVCO can even achieve 4.6 dB lower phase noise than its single-phase counterpart at 3-MHz offset. Optimized capacitive coupling combined with source inductive enhance-swing technique enables low power and low phase noise simultaneously. The QVCO achieves a measured phase noise of -132.2 dBc/Hz @ 3-MHz offset with a center frequency of 5.6 GHz and consumes 4.2 mW from a 0.6-V supply. This performance corresponds to a figure-of-merit (FoM) of 191.4 dB. Due to the intrinsic phase shift in the proposed quadrature-coupling path, the problem associated with ±90° phase ambiguity between the quadrature outputs has been avoided. The QVCO RFIC is implemented in a 0.13nμm CMOS process with core area of 0.6 × 0.8 mm2.

On the low-power design, stability improvement and frequency estimation of the CMOS ring oscillator

Abstract: In this paper, a simple method allowing optimization of the CMOS ring oscillator frequency dispersion and power consumption is discussed. It is shown, that for range of tens of MHz and less, the power consumption and variation of the frequency can be considerably reduced by using 3-stage, resistively coupled ring oscillator, with minimum channel width W and large channel length L MOS transistors. In addition, a simple analysis allowing to estimate the oscillator frequency from the process and transistor parameter values is provided.

A Low-Power Wideband Transmitter Front-End Chip for 80 GHz FMCW Radar Systems With Integrated 23 GHz Downconverter VCO

Abstract: A low-power FMCW 80 GHz radar transmitter front-end chip is presented, which was fabricated in a SiGe bipolar production technology ( fT=180 GHz, fmax=250 GHz ). Additionally to the fundamental 80 GHz VCO, a 4:1-frequency divider (up to 100 GHz), a 23 GHz local oscillator (VCO) with a low phase noise of -112 dBc/Hz (1 MHz offset), a PLL-mixer and a static frequency divider is integrated together with several output buffers. This chip was designed for low power consumption (in total <; 0.5 W, i.e., 100 mA at 5 V supply voltage), which is dominated by the 80 GHz VCO due to the demands for high output power (≈ 12 dBm) and low phase noise (minimum -97 dBc/Hz at 1 MHz offset) within the total wide tuning range from 68 GHz to 92.5 GHz (Δf = 24.5 GHz). Measurements of the double-PLL system at 80 GHz showed a low phase noise of -88 dBc/Hz at 10 kHz offset frequency.

A 1-mW 1.13–1.9 GHz CMOS LC VCO Using Shunt-Connected Switched-Coupled Inductors

Abstract: A low-power wideband LC VCO has been designed and implemented in a 90-nm CMOS technology. Wide tuning range, low phase noise and low power consumption are achieved thanks to the adopted LC tank, which makes use of shunt-connected switched-coupled inductors and a proper arrangement of varactors. The shunt-connected switched-coupled inductors provide coarse tuning and phase noise optimization without using amplitude calibration loop or trimming of the bias current. The proposed varactors configuration employs accumulation mode thin and thick MOS devices, which has been differently biased to obtain tuning range maximization along with minimization of the amplitude-to-phase noise conversion. The LC-tank topology and inductor layout have been properly designed to attain a die area comparable to a single-inductor VCO, taking advantage of the inductors mutual coupling. The VCO exhibits a phase noise at 1-MHz offset frequency lower than -114 dBc/Hz over the entire tuning range and achieves -126.1 dBc/Hz at 1.2 GHz. It provides a tuning range of 51% from 1.13 GHz to 1.9 GHz with a tuning voltage ranging from 0 to 1.2 V. Despite a very low current consumption, which is 0.88 mA from a 1.2-V supply, the proposed VCO has the outstanding PFTN figure-of-merit of 10. The VCO core die area is 0.5 mm2.