Showing papers on "Voltage-controlled oscillator published in 2014"

A CMOS 210-GHz Fundamental Transceiver With OOK Modulation

Abstract: This paper presents a 210-GHz transceiver with OOK modulation in a 32-nm SOI CMOS process (fT/fmax= 250/320 GHz). The transmitter (TX) employs a 2 × 2 spatial combining array consisting of a double-stacked cross-coupled voltage controlled oscillator (VCO) at 210 GHz with an on-off-keying (OOK) modulator, a power amplifier (PA) driver, a novel balun-based differential power distribution network, four PAs, and an on-chip 2 × 2 dipole antenna array. The noncoherent receiver (RX) utilizes a direct detection architecture consisting of an on-chip antenna, a low-noise amplifier (LNA), and a power detector. The VCO generates measured -13.5-dBm output power, and the PA shows a measured 15-dB gain and 4.6-dBm Psat. The LNA exhibits a measured in-band gain of 18 dB and minimum in-band noise figure (NF) of 11 dB. The TX achieves an EIRP of 5.13 dBm at 10 dB back-off from saturated power. It achieves an estimated EIRP of 15.2 dBm when the PAs are fully driven. This is the first demonstration of a fundamental frequency CMOS transceiver at the 200-GHz frequency range.

Electromagnetic sensing touch screen

Abstract: The present invention discloses an electromagnetic sensing touch screen, which includes a display panel, a sensing capacitor matrix, select units, voltage controlled oscillators (VCOs), digital potentiometers, EM (electromagnetic) wave receive/detection units, a standard EM wave transmit unit and a control unit. A single detection unit consists of a corresponding select unit, VCO, digital potentiometer and EM wave receive/detection unit. The control unit drives the standard EM wave transmit unit to transmit standard EM wave, and further controls the EM wave receive/detection units to receive sensed capacitance values from the sensing capacitor matrix in a scanning manner. As a result, each EM wave receive/detection unit generates a respective detection signal for determining the location of the finger(s) and checking how the finger(s) approaches to or actually touches the sensing capacitor matrix, thereby generating finger location information and implementing the multipoint touch and display function.

A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration

Abstract: This paper presents a low-jitter, low-power and a small-area injection-locked all-digital PLL (IL-ADPLL). It consists of a dual-loop and a dual-VCO architecture in which one VCO (Replica) is placed in a TDC-less synthesizable ADFLL to provide continuous tracking of voltage and temperature variations. The other VCO (main) shares the control voltage with the replica VCO but is placed outside the loop and is injection-locked to lower its jitter and accurately set its frequency to the desired one. This approach avoids timing problems in the conventional ILPLL since the injection-locked VCO is placed outside the feedback loop. It also achieves a low power and a small area, due to the absence of a power hungry TDC and an area-consuming loop filter, while tracking any PVT variations. The IL-ADPLL is implemented in a 65 nm CMOS process and measurement results show that it achieves a 0.7ps RMS jitter at 1.2 GHz while having 1.6 mW and 0.97 mW power consumption with and without intermittent operation resulting in an FOM of -243 dB. It also consumes an area of only 0.022 mm2 resulting in the best performance-area trade-off system presented up-to-date.

A Deterministic Digital Background Calibration Technique for VCO-Based ADCs

Abstract: This paper presents a digital background calibration technique to realize a linear voltage-controlled-oscillator (VCO) based ADC. The distortion caused due to the VCO's nonlinear tuning characteristics is eliminated by introducing an inverse voltage-to-frequency transfer function in the signal path. The proposed calibration unit runs in the background and detects the inverse transfer function using a highly digital frequency locked loop. Like many other VCO-based ADCs, the proposed technique does not require analog building blocks such as operational amplifiers, multi-bit feed-back DACs etc., and retains the scaling friendly properties. Implemented in a 90 nm CMOS process, the on-chip calibration improves SNDR of an open-loop VCO-based ADC from 46 dB to more than 73 dB in 5 MHz signal bandwidth while consuming 4.1 mW power. The ADC achieves a figure-of-merit of 91-112 fJ/conv-step for different input frequencies.

A 1.2-pJ/bit 16-Gb/s 60-GHz OOK Transmitter in 65-nm CMOS for Wireless Network-On-Chip

Abstract: This paper presents a high-efficiency 60-GHz on-off keying (OOK) transmitter (TX) designed for wireless network-on-chip applications. Aiming at an intra-chip commu- nication distance of 20 mm, the TX consists of a drive amplifier (DA), a high-speed OOK modulator, and a transformer-coupled voltage-controlled oscillator. For high efficiency, a common-source topology with a drain-to-gate neutralization technique is chosen for the DA. A detailed mathematical design methodology is de- rived for the neutralization technique. The bulk-driven OOK modulator employs a novel dual feedthrough cancellation tech- nique, resulting in a 30-dB on-off ratio. Fabricated in a 65-nm bulk CMOS process, the TX consumes only 19 mW from a 1-V supply, and occupies an active area of 0.077 mm . A maximum modulation data rate of 16 Gb/s with 0.75-dBm output power is demonstrated through measurements, which translates to a bit-energy efficiency of 1.2 pJ/bit. Index Terms—Bulk driven, CMOS, drive amplifier (DA), low power, millimeter wave, modulator, neutralization, on-off keying (OOK), transmitter (TX), voltage-controlled oscillator (VCO), wireless network-on-chip (WiNoC).

A W-Band Low-Noise PLL With a Fundamental VCO in SiGe for Millimeter-Wave Applications

Abstract: A W-band fundamental phase-locked loop (PLL) is designed and fully integrated to achieve high output power and low noise in a 0.13-μm SiGe BiCMOS process. A PLL with a fundamental voltage-controlled oscillator (VCO) is chosen after comparing several frequency-synthesizer architectures. Local oscillator (LO) generation and LO distribution are also considered. The employed free-running VCO achieves a tuning range from 92.5 to 102.5 GHz (8.3%), an output power of 6 dBm, and a phase noise of -124.5 dBc/Hz at 10-MHz offset. The locking range of the PLL is from 92.7 to 100.2 GHz, and the phase noise is -102 dBc/Hz at 1-MHz offset. The root mean square jitter integrated from 1 MHz to 1 GHz is 71 fs. Finally, the figure-of-merit for VCOs is discussed.

A Silicon-Based 0.3 THz Frequency Synthesizer With Wide Locking Range

Abstract: A 300 GHz frequency synthesizer incorporating a triple-push VCO with Colpitts-based active varactor (CAV) and a divider with three-phase injection is introduced. The CAV provides frequency tunability, enhances harmonic power, and buffers/injects the VCO fundamental signal from/to the divider. The locking range of the divider is vastly improved due to the fact that the three-phase injection introduces larger allowable phase change and injection power into the divider loop. Implemented in 90 nm SiGe BiCMOS, the synthesizer achieves a phase-noise of -77.8 dBc/Hz (-82.5 dBc/Hz) at 100 kHz (1 MHz) offset with a crystal reference, and an overall locking range of 280.32-303.36 GHz (7.9%).

Design and Analysis of Wide Frequency-Tuning-Range CMOS 60 GHz VCO by Switching Inductor Loaded Transformer

Abstract: To provide wide frequency tuning range (FTR) with compact implementation area, a new inductive tuning method is introduced in this paper for CMOS 60 GHz voltage controlled oscillator (VCO). The inductive tuning is based on a switching inductor-loaded transformer by configuring different current return-paths in the secondary coil of the transformer. Different from previous inductive tuning methods, the proposed VCO topology can achieve wide FTR for multiple sub-bands at 60 GHz within compact area by only one transformer. Two 60 GHz VCOs are demonstrated in 65 nm CMOS with design targets for the maximum FTR and the balanced phase noise in each sub-band, respectively. As measured by experiments, the first VCO (asymmetric) achieves a wide FTR of 25.8% from 51.9 to 67.3 GHz with phase noise variation of ±8.2 dB ( -90.2 to -106.7 dBc/Hz at 10 MHz offset) in all sub-bands; and the second VCO (symmetric) realizes a low phase noise variation of ±2.5 dB ( -105.9 to -110.8 dBc/Hz at 10 MHz offset) in all sub-bands with a FTR of 14.2% from 57.0 GHz to 65.5 GHz.

14.8 A 247-to-263.5GHz VCO with 2.6mW peak output power and 1.14% DC-to-RF efficiency in 65nm Bulk CMOS

Abstract: Signal generation at mm-Wave-to-THz frequencies is attractive because of its applications in bio-sensing, spectroscopy, detection of concealed weapons, as well as high-data-rate communication. CMOS is considered a potential platform to implement a low-cost and high-yield signal generation solution at this frequency range. Despite continuous scaling, effective fmax of active devices is not high enough and hence either harmonic oscillators or frequency multipliers are employed for high-frequency signal generation. In recent CMOS VCO designs, reasonable power levels (~1mW) and tuning range (~10GHz) have been reported at around 300GHz but with very low DC-to-RF efficiency (<;0.4%), which is undesirable for portable applications [1,4]. Moreover, power-level fluctuation is more than 3dB across the frequency range [1]. In this work, we introduce a scalable VCO architecture that efficiently generates and extracts the 2nd harmonic at 256GHz and hence simultaneously achieves high tuning range (16GHz), high output power (2.6mW), high DC-RF efficiency (1.14%), and low phase noise (-94dBc/Hz to -85dBc/Hz at 1MHz offset frequency across the tuning range). When compared to published state-of-the-art, this work demonstrates the highest output power, tuning range, and DC-to-RF efficiency, and the lowest phase noise among all CMOS VCOs above 200GHz.

15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO

Abstract: Due to the high supply sensitivity of ring voltage-controlled oscillators (RVCOs) ([oscillation frequency change %] / [VDD change %] typically lies in the range from 1 to 2 [1]), an LDO has to provide over 40dB power-supply-rejection ratio (PSRR) to maintain VCO phase noise. However, the voltage dropout of an LDO consumes extra power and voltage headroom, which is unacceptable in low-voltage design. Moreover, the device noise from the LDO degrades the phase-noise performance. Recently published works [1-5] employ analog compensation techniques to lower supply sensitivity, and [2] incorporates a hybrid background calibration scheme for robustness. However, the additional current sources and active devices embedded in the oscillator [1-5] increase power and noise. In this work, a DCO with passive devices and all-digital calibration mitigates supply sensitivity under PVT variation, while maintaining phase noise and power consumption. The digital background-calibration logic regulates the oscillator supply to an optimally insensitive point by monitoring a digital loop filter (DLF) code, leveraging an advantage of an ADPLL [6].

Density Profile and Fluctuation Measurements by Microwave Reflectometry on EAST

Abstract: A microwave reflectometry system operating in the V-band frequency with extraordinary mode polarization has been developed on the EAST tokamak. The reflectometry system, using a voltage-controlled oscillator (VCO) source driven by an arbitrary waveform generator with high temporal resolution, can operate for the density profile measurement. The result of the bench test shows that the output frequency of the VCO has a linear dependence on time. The dispersion of reflectometry system is determined and reported in this paper. The evolution of a pedestal density profile during the L-H transition is observed by the reflectometry in H-mode discharges on EAST tokamak. A frequency synthesizer is used to replace the VCO as microwave source for density fluctuation measurements. The level of density fluctuation in the pedestal shows an abrupt decrease when the plasma enters into H-mode. A coherent mode with a frequency of about 100 kHz is observed and the mode frequency decreases gradually as the pedestal evolves.

A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector

Abstract: A low-noise divider-less PLL, employing a subsampling locked loop, samples the VCO output by a digital pulse-width modulator (DPWM) to perform fractional-N operation. The frequency synthesizer achieves a low in-band phase noise of -112 dBc/Hz at a 2.3 GHz output frequency. The analysis for the frequency synthesizer, especially for the nonlinear characteristics of the circuits, is proposed. Fabricated in a 0.18 μm CMOS technology, the frequency synthesizer consumes 9.6 mA and achieves figure-of-merit of -239.1 dB, corresponding to 266 fs rms jitter.

Truly Random Number Generator Based on a Ring Oscillator Utilizing Last Passage Time

Abstract: This brief covers the design and fabrication of a ring oscillator-based truly random number generator (TRNG), which was fabricated in 013- $\mu\hbox{m}$ CMOS technology The randomness originates from the phase noise in a ring oscillator Timing jitter resulting from crossing the threshold multiple times, ie, last passage time (LPT), is exploited Previously, the jitter model was developed and applied to the core delay cell of the slow VCO, part of the ring oscillator, where a slow slew rate phase was introduced to greatly increase phase noise In this brief, the successful design of the entire TRNG was performed This includes designing the circuit to avoid introducing correlation in the TRNG Toward this end, novel timing circuitry is designed to properly control both the beginning and termination of this slow slew rate phase by tapping into the previous stage's output 1/f noise also has to be minimized Furthermore, the entire TRNG is now designed/implemented and fabricated, and experimental results are shown The fabricated ring oscillator was shown to possess a timing jitter of 15 ns Simulation under PVT variations of the entire cell shows that jitter variations are within 30%, showing that the designed control circuit was able to perform under such PVT variations Entropy simulation with power supply variations applied to the TRNG was also run to assess its effectiveness as the biasing condition is changing The randomness of the entire TRNG was assessed by applying the National Institute of Standards and Technology (NIST) tests On those tests recommended by NIST to have longer bit streams, additional test measurements were performed on bit streams with increased length Entropy tests for 20 k, 200 k, and 400 k measured bits were performed, resulting in entropy values all close to 1

300-GHz InP HBT Oscillators Based on Common-Base Cross-Coupled Topology

Abstract: Two fundamental-mode oscillators operating around 300 GHz, a fixed-frequency oscillator and a voltage-controlled oscillator (VCO), have been developed in this work based on a 250-nm InP heterojunction bipolar transistor (HBT) technology. Both oscillators adopted the common-base configuration for the cross-coupled oscillator core, providing higher oscillation frequency compared to the conventional common-emitter cross-coupled topology. The fabricated fixed-frequency oscillator and the VCO exhibited oscillation frequency of 305.8 GHz and 298.1-316.1 GHz (18-GHz tuning range) at dc power dissipation of 87.4 and 88.1 mW, respectively. The phase noise of the fixed-frequency oscillator was measured to be -116.5 dBc/Hz at 10 MHz offset. The peak output power of 5.3 dBm (3.8% dc-to-RF efficiency) and 4.7 dBm (3.2% dc-to-RF efficiency) were respectively achieved for the two oscillators, which are the highest reported power for a transistor-based single oscillator beyond 200 GHz.

Development of frequency modulated continuous wave reflectometer for electron density profile measurement on the HL-2A tokamak

Abstract: The frequency modulated continuous wave reflectometer was developed for the first time on the HL-2A tokamak. The system utilizes a voltage controlled oscillator and an active multiplier for broadband coverage and detects as heterodyne mode. Three reflectometers have been installed and operated in extraordinary mode polarization on HL-2A to measure density profiles at low field side, covering the Q-band (33–50 GHz), V-band (50–75 GHz), and W-band (75–110 GHz). For density profile reconstruction from the phase shift of the probing wave, a corrected phase unwrapping method is introduced in this article. The effectiveness of the method is demonstrated. The density profile behavior of a fast plasma event is presented and it demonstrates the capability of the reflectometer. These diagnostics will be contributed to the routine density profile measurements and the plasma physics study on HL-2A.

Memristor-based voltage-controlled relaxation oscillators

Abstract: This paper introduces two voltage-controlled memristor-based reactance-less oscillators with analytical and circuit simulations. Two different topologies which are R-M and M-R are discussed as a function of the reference voltage where the generalized formulas of the oscillation frequency and conditions for oscillation for each topology are derived. The effect of the reference voltage on the circuit performance is studied and validated through different examples using PSpice simulations. A memristor-based voltage-controlled oscillator VCO is introduced as an application for the proposed circuits which is nano-size and more efficient compared to the conventional VCOs. Copyright © 2013 John Wiley & Sons, Ltd.

A 120 GHz Fully Integrated 10 Gb/s Short-Range Star-QAM Wireless Transmitter With On-Chip Bondwire Antenna in 45 nm Low Power CMOS

Abstract: In this paper, a fully integrated $D$ -band transmitter with on-chip dipole bondwire antenna implemented in 45 nm low-power CMOS is presented. The purpose of this 120 GHz wireless connector is to provide a high-speed short-range wireless communication link. On-chip frequency generation, insensitive to VCO pulling, is integrated together with a direct carrier quadrature vector modulator, ASK modulator, four-stage differential transformer-coupled power amplifier, and bondwire antenna. A $2^{9}-1$ -bit PRBS generator, capable of generating three parallel bit streams at a clock frequency of 8 GHz, is integrated on the same chip for measurement purposes. The transmitter is capable of efficiently generating BPSK, QPSK, and Star-QAM modulation formats. Data transmission over a distance up to 1 m is achieved for data rates as high as 2 Gb/s. For shorter distances, data rates up to 10 Gb/s are measured.

A 0.4-V, 90 $\sim$ 350-MHz PLL With an Active Loop-Filter Charge Pump

Abstract: A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly reduced reference spurs. Its voltage-controlled oscillator (VCO) is designed with the body-bias technique and includes an automatic frequency calibration circuit that provides low VCO gain and wide tuning range. The PLL output frequency can be tuned from 90 to 350 MHz. At 350-MHz output, the PLL consumes 109 $\mu\hbox{W}$ , which corresponds to the power efficiency of 0.31 mW/GHz.

Frequency tuning for lc circuits

Abstract: Apparatus and methods are disclosed related to tuning a resonant frequency of an LC circuit. In some implementations, the LC circuit can be embodied in a low noise amplifier (LNA) of a receiver. The receiver can include a component configured to generate an indicator of received signal strength indication (RSSI) of a radio frequency (RF) signal received by the receiver. A control block can adjust the resonant frequency of the LC circuit based at least in part on the indicator of RSSI. As another example, the receiver can include an oscillator, such as a VCO, separate from the LC circuit that can be used to tune the resonant frequency of the LC circuit. These apparatus can compensate for variation in a zero imaginary component of an impedance across the LC circuit.

9.5 A 1.2nJ/b 2.4GHz receiver with a sliding-IF phase-to-digital converter for wireless personal/body-area networks

Abstract: This paper presents an ultra-low-power (ULP) 2.4GHz RX for short-range wireless personal and body-area networks. In such applications, the RF transceiver consumes up to 90% of the total battery energy in a remote sensor node. In order to extend the operation lifetime, it is a primary design goal for such transceivers to improve the energy efficiency, expressed as power consumption/data-rate, to below 1nJ/bit. Although energy-detection or superregenerative ASK RXs [1] are very efficient, they are vulnerable to interference and this leads to a poor quality of the wireless link in a crowded 2.4GHz ISM band. On the other hand, FSK/PSK-type modulations are popular in the target applications because of their power-efficient hardware and higher immunity to interference. They are also widely adopted in many short-range wireless standards like IEEE802.15.4 and Bluetooth Smart. Thanks to the constant-envelope nature of FSK/PSK-type modulations, e.g., HS-OQPSK, they only modulate data on the carrier frequency or phase, so the TX hardware can be simplified, while the efficiency can be enhanced by driving the circuits into a saturated mode, e.g., PLL-based FSK TXs [2,5]. Similarly, in the RX counterpart, instead of processing the signal in the I/Q domain, it can be demodulated in the phase domain by using a phase-ADC [3]. However, such approach still requires a power-hungry high-frequency multi-phase LO generation and “2-dimensional” downconversion and filtering circuits. In the single-channel RX of [4], the VCO is part of the carrier-recovery and phase-demodulation loop. Therefore, the VCO frequency can be easily “pulled away” by an interferer, and the RX has a poor sensitivity because phase noise is deteriorated by the signal chain when input level is low.

High Efficiency 293 GHz Radiating Source in 65 nm CMOS

Abstract: This letter presents a J-band radiating source (284-301 GHz) based on a differential Colpitts oscillator with an on-chip antenna in 65 nm CMOS. The source radiates the third harmonic of the oscillation frequency, which is also generated in the voltage controlled oscillator (VCO) itself due to its large voltage signal. An integrated loop antenna serves also as the load inductance at the drains of the VCO transistors, acting as a choke at the fundamental and matched antenna at the third harmonic. The antenna has a directivity above $+9~{\rm dBi}$ across the tuning range. This frequency source has a DC-to-RF radiated power efficiency of 2.8%, a radiated power of $-2.7~{\rm dBm}$ and an EIRP of $+6.4~{\rm dBm}$ , taking a silicon area of only $0.26~{\rm mm}^{2}$ .

A 28 GHz Hybrid PLL in 32 nm SOI CMOS

Abstract: A hybrid PLL is introduced, which features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. In addition to the analog proportional path, the PLL includes a set of digital proportional path controls, so that the two approaches can be experimentally compared. At 28 GHz the RMS jitter is 199 fs (1 MHz to 1 GHz), phase noise is -110 dBc/Hz at 10 MHz offset. The 14 × 160 μm2 32 nm SOI CMOS PLL locks from 23.8 to 30.2 GHz, and draws 31 mA from a 1 V supply.

21.5-to-33.4 GHz Voltage-Controlled Oscillator Using NMOS Switched Inductors in CMOS

Abstract: To demonstrate the applicability of NMOS switched variable inductors in the millimeter wave frequencies, a 21.5 to 33.4 GHz wide tuning range LC voltage-controlled oscillator (LC-VCO) with frequency tunable output buffers that uses variable inductors is reported. The measured phase noise at 10 MHz offset of VCO fabricated in a 65 nm bulk CMOS process varies from ${-}117$ to ${-}109$ dBc/Hz. The oscillator core consumes 4 or 6 mA from a 1.2 V power supply. These correspond to a record 43.3% tuning range. ${\rm FOM}_{\rm T}$ ranges from ${-}191.7$ to ${-}181.9$ dBc/Hz. With tunable output buffers, the measured signal output power is above ${-}15$ dBm across the entire frequencies.

An analytical formulation for phase noise in MEMS oscillators.

Abstract: In recent years, there has been much interest in the design of low-noise MEMS oscillators. This paper presents a new analytical formulation for noise in a MEMS oscillator encompassing essential resonator and amplifier nonlinearities. The analytical expression for oscillator noise is derived by solving a second-order nonlinear stochastic differential equation. This approach is applied to noise modeling of an electrostatically addressed MEMS resonator-based square-wave oscillator in which the resonator and oscillator circuit nonlinearities are integrated into a single modeling framework. By considering the resulting amplitude and phase relations, we derive additional noise terms resulting from resonator nonlinearities. The phase diffusion of an oscillator is studied and the phase diffusion coefficient is proposed as a metric for noise optimization. The proposed nonlinear phase noise model provides analytical insight into the underlying physics and a pathway toward the design optimization for low-noise MEMS oscillators.

2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS

Abstract: High-speed transceivers embedded inside FPGAs require software-programmable clocking circuits to cover a wide range of data rates across different channels [1]. These transceivers use high-frequency PLLs with LC oscillators to satisfy stringent jitter requirements at increasing data rates. However, the large area of these oscillators limits the number of independent LC-based clocking sources and reduces the flexibility offered by the FPGA. A ring-based PLL occupies smaller area but produces higher jitter. With injection-locking (IL) techniques [2-3], ring-based oscillators achieve comparable performance with their LC counterparts [4-5] at frequencies below 10GHz. Moreover, addition of a PLL to an injection-locked VCO (IL-PLL) provides injection-timing calibration and frequency tracking against PVT [3,5]. Nevertheless, applying injection-locking techniques to high-speed ring oscillators in deep submicron CMOS processes, with high flicker-noise corner frequencies at tens of MHz, poses a design challenge for low-jitter operation. Shown in Fig. 2.8.1, injection locking can be modeled as a single-pole feedback system that achieves 20dB/dec of in-band noise shaping against intrinsic VCO phase noise over a wide bandwidth [6]. As a consequence, this technique suppresses the 1/f2 noise of the VCO but not its 1/f3 noise. Note that the conventional IL-PLL is capable of shaping the VCO in-band noise at 40dB/dec [6]; however, its noise shaping is limited by the narrow PLL bandwidth due to significant attenuation of the loop gain by injection locking. To achieve wideband 2nd-order noise shaping in 20nm ring oscillators, we present a circuit technique that applies pulse-position-modulated (PPM) injection through feedback control.

A Low-Voltage and Low-Power 3-GHz CMOS LC VCO for S-Band Wireless Applications

Abstract: A fully integrated 018- $$\upmu \hbox {m}$$ μ m CMOS LC-tank voltage-controlled oscillator (VCO) suitable for low-voltage and low-power S-band wireless applications is proposed in this paper In order to meet the requirement of low voltage applications, a differential configuration with two cross-coupled pairs by adopting admittance-transforming technique is employed By using forward-body-biased metal oxide semiconductor field effect transistors, the proposed VCO can operate at 04 V supply voltage Despite the low power supply near threshold voltage, the VCO achieves wide tuning range by using a voltage-boosting circuit and the standard mode PMOS varactors in the proposed oscillator architecture The simulation results show that the proposed VCO achieves phase noise of $$-$$ - 1201 dBc/Hz at 1 MHz offset and 393 % tuning range while consuming only $$594~\upmu \hbox {W}$$ 594 μ W in 04 V supply Figure-of-merit with tuning range of the proposed VCO is $$-$$ - 1921 dB at 3 GHz

Low-noise and broadband optical frequency comb generation based on an optoelectronic oscillator

Abstract: A novel scheme to generate broadband high-repetition-rate optical frequency combs and low phase noise microwave signals simultaneously is proposed and experimentally demonstrated. By incorporating an optical frequency comb generator in an optoelectronic oscillator loop, more than 200 lines are generated for a 25 GHz optical frequency comb, and the single-sideband phase noise is as low as −122 dBc/Hz at 10 kHz offset for the 25 GHz microwave signal. 10 and 20 GHz optical frequency combs and microwave signals are also generated. Unlike the microwave frequency synthesizer, the phase noise of the microwave signals generated by this new scheme is frequency independent.

Comparison of Optical Self-Phase Locked Loop Techniques for Frequency Stabilization of Oscillators

Abstract: Self-phase locked loop (SPLL) through long optical delay lines is investigated for improving the phase noise of the optoelectronic oscillator (OEO) and the voltage-controlled oscillator (VCO). This paper features analytical modeling of close-in to carrier phase noise of oscillators employing SPLL technique using single and multiple delay loops. Experimental results are also provided to verify the analytical modeling and explore critical circuit design parameters to achieve substantial phase noise reduction. Performance comparison is presented for SPLL using electrical phase shifter, Mach-Zehnder modulator (MZM)-based phase shifting, and electrical VCO. Phase noise reduction of 65 dB at 1-kHz offset is achieved for an electrical VCO employing a dual-loop SPLL with 3- and 5-km optical fiber delay lines, whereas the phase locking based on MZM and electrical phase shifter provided 20- and 38-dB reductions at 1-kHz offset for an OEO, respectively.

An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS

Abstract: As an alternative to the conventional dual-loop architecture, reference-less CDR architectures have become more popular in industry because of their simplicity and flexibility [1-5]. However, the robustness of the transition between frequency acquisition and phase locking is always a concern, particularly for the linear CDR, which has an extremely limited capture range. Many works, based mainly on the Pottbacker frequency detector (FD) [1], have been reported. In [3] the capture range of the FD is only ±2.4% at 20Gb/s with no capacitor bank in the VCO; in [4] the capture range of the FD is about ±6.4% at 2.75Gb/s, with an 8b resolution of the capacitor bank in the VCO; in [5] the capture range is ±15% at 10Gb/s, with an 11b resolution of the capacitor bank. Thus the Pottbacker FD inherently suffers from a limited capture range, requiring a dedicated FD and a stringent tradeoff between the CDR capture range and the number of VCO bands. In the presence of input jitter and phase-detector (PD) non-idealities, it is difficult to design an architecture where the resolution of the capacitor bank and the turnoff mechanism can guarantee that the VCO frequency will eventually fall within the pull-in range of the CDR.

A 105-GHz VCO With 9.5% Tuning Range and 2.8-mW Peak Output Power in a 65-nm Bulk CMOS Process

Abstract: To demonstrate high tuning range and large output power, we propose a loop of coupled oscillators in this work. Two different tuning mechanisms are simultaneously exploited. First, each core oscillator is tuned using a variable capacitor. Next, by controlling the phase/delay between the coupled oscillators, the entire loop dynamics, and hence, its frequency is tuned. In this paper, we analyze a loop of “n” coupled oscillators using Adler's equation and derive the expression for the maximum tuning range. Perturbation analysis is used to study the stability conditions of the loop of coupled system. The analysis is extended toward a nested loop of coupled oscillators. The activity condition from two-port theory is used to squeeze maximum power out of active devices. The proposed system is designed and implemented using four coupled Colpitts voltage-controlled oscillators (VCOs) in a 65-nm bulk CMOS process. The VCO achieves continuous tuning range of 9.5% at the center frequency of 105 GHz with the peak output power of 2.8 mW. The circuit consumes 54 mW from a 1.2-V supply. To the best of our knowledge, this VCO has the highest output power and tuning range among all the CMOS oscillators at or above 100 GHz.