Showing papers on "Voltage-controlled oscillator published in 2016"
TL;DR: This work presents a highly integrated 57-64 GHz 4-channel receiver 2-channel transmitter chip targeting short range sensing and large bandwidth communications that is housed in an embedded wafer level ball grid array package.
Abstract: This work presents a highly integrated 57–64 GHz 4-channel receiver 2-channel transmitter chip targeting short range sensing and large bandwidth communications. The chip is housed in an embedded wafer level ball grid array package. The package includes 6 integrated patch antennas realized with a metal redistribution layer. The receiver patch antennas have a combined antenna gain of $\approx 10$ dBi while each transmitter antenna has a gain of $\approx ~6$ dBi. The chip features a wide tuning range integrated VCO with a measured phase noise lower than −80 dBc/Hz at 100 kHz offset. Each of the differential transmitter channels shows a measured output power of 2–5 dBm over the complete frequency range. In addition, one transmitter channel features a modulator that can be digitally programmed to operate in either radar or communication mode. Each of the receiver channels has a measured conversion gain of 19 dB, a single-sideband noise figure of less than 10 dB and an input referred 1 dB compression point of less than 10 dBm. With all channels turned on the chip consumes a current of 300 mA from a 3.3 V supply. The functionality of the chip is demonstrated for both sensing and short range wireless communications.
147 citations
TL;DR: A mm-wave frequency generation technique that improves its phase noise (PN) performance and power efficiency and third-harmonic boosting and extraction techniques are proposed and applied to the frequency generator.
Abstract: This paper proposes a mm-wave frequency generation technique that improves its phase noise (PN) performance and power efficiency. The main idea is that a fundamental 20 GHz signal and its sufficiently strong third harmonic at 60 GHz are generated simultaneously in a single oscillator. The desired 60 GHz local oscillator (LO) signal is delivered to the output, whereas the 20 GHz signal can be fed back for phase detection in a phase-locked loop. Third-harmonic boosting and extraction techniques are proposed and applied to the frequency generator. A prototype of the proposed frequency generator is implemented in digital 40 nm CMOS. It exhibits a PN of $-100\;\text{dBc/Hz}$ at 1 MHz offset from 57.8 GHz and provides 25% frequency tuning range (TR). The achieved figure-of-merit (FoM) is between 179 and 182 dBc/Hz.
109 citations
TL;DR: This paper applies an idea of coupling multiple oscillators to reduce phase noise (PN) to beyond the limit of what has been practically achievable so far in a bulk CMOS technology to demonstrate for the first time an RF oscillator that meets the most stringent PN requirements of cellular basestation receivers while abiding by the process technology reliability rules.
Abstract: In this paper, we exploit an idea of coupling multiple oscillators to reduce phase noise (PN) to beyond the limit of what has been practically achievable so far in a bulk CMOS technology. We then apply it to demonstrate for the first time an RF oscillator that meets the most stringent PN requirements of cellular basestation receivers while abiding by the process technology reliability rules. The oscillator is realized in digital 65-nm CMOS as a dual-core LC-tank oscillator based on a high-swing class-C topology. It is tunable within 4.07–4.91 GHz, while drawing 39–59 mA from a 2.15 V power supply. The measured PN is $-$ 146.7 dBc/Hz and $-$ 163.1 dBc/Hz at 3 MHz and 20 MHz offset, respectively, from a 4.07 GHz carrier, which makes it the lowest reported normalized PN of an integrated CMOS oscillator. Straightforward expressions for PN and interconnect resistance between the cores are derived and verified against circuit simulations and measurements. Analysis and simulations show that the interconnect resistance is not critical even with a 1% mismatch between the cores. This approach can be extended to a higher number of cores and achieve an arbitrary reduction in PN at the cost of the power and area.
90 citations
TL;DR: A low-jitter, ring-type voltage-controlled oscillator (VCO)-based injection-locked clock multiplier (ILCM) with a continuous frequency-tracking loop (FTL) for process-voltagetemperature (PVT)-calibration is presented.
Abstract: A low-jitter, ring-type voltage-controlled oscillator (VCO)-based injection-locked clock multiplier (ILCM) with a continuous frequency-tracking loop (FTL) for process-voltage-temperature (PVT)-calibration is presented. Using a single replica-delay cell of the VCO that provides the intrinsic phase information of the free-running VCO, the proposed FTL can continuously track and correct frequency drifts. Therefore, the proposed ILCM can calibrate real-time frequency drifts due to voltage or temperature variations as well as static frequency deviations due to process variations. Since the FTL provided an additional filtering of in-band VCO noise, the ILCM was able to achieve excellent jitter performance over the PVT variations, while it was based on a ring-VCO. The proposed ILCM was fabricated in a 65 nm CMOS process. When injection locked, the RMS-jitter integrated from 10 kHz to 40 MHz of the 1.20 GHz output signal was 185 fs. The proposed PVT-calibrator regulated the degradations of jitter to less than 5% and 7% over temperatures and supply voltages, respectively. The active area was $\text {0.06 mm}^{2}$ and total power consumption was 9.5 mW.
80 citations
TL;DR: A self-referenced VCO-based temperature sensor with reduced supply sensitivity and a novel sensing technique in which temperature information is acquired by evaluating the ratio of the output frequencies of two ring oscillators, designed to have different temperature sensitivities, thus avoiding the need for an external frequency reference.
Abstract: A self-referenced VCO-based temperature sensor with reduced supply sensitivity is presented. The proposed sensor converts temperature information to frequency and then into digital bits. A novel sensing technique is proposed in which temperature information is acquired by evaluating the ratio of the output frequencies of two ring oscillators, designed to have different temperature sensitivities, thus avoiding the need for an external frequency reference. Reduced supply sensitivity is achieved by employing the voltage dependence of junction capacitance, thus avoiding the overhead of a voltage regulator. Fabricated in a 65 nm CMOS process, the prototype can operate with supply voltages ranging from 0.85 V to 1.1 V. It achieves supply sensitivity of 0.034 °C/mV and an inaccuracy of ±0.9 °C and ±2.3 °C from 0 to 100 °C after 2-point calibration, with and without static nonlinearity correction, respectively. The proposed sensor achieves 0.3 °C resolution, and a resolution FoM of 0.3 nJK2. The prototype occupies a die area of 0.004 mm2.
77 citations
TL;DR: In this paper, a low frequency relaxation oscillator is designed using a super-capacitor and an accurate analytical expression for the oscillation frequency is derived based on a fractional-order super-Capacitor model composed of a resistance in series with a Constant Phase Element (CPE) whose pseudo capacitance and dispersion coefficient are determined using impedance spectroscopy measurements.
Abstract: A low frequency relaxation oscillator is designed using a super-capacitor. An accurate analytical expression for the oscillation frequency is derived based on a fractional-order super-capacitor model composed of a resistance in series with a Constant Phase Element (CPE) whose pseudo-capacitance and dispersion coefficient are determined using impedance spectroscopy measurements. Experimental results confirm our theoretical analysis.
71 citations
TL;DR: In this paper, an ultra-high-speed fractional-N$ frequency divider and a highly linear phase-frequency detector (PFD) are integrated into a high-frequency SiGe bipolar technology.
Abstract: A millimeter-wave (mm-wave) frequency synthesizer is presented focusing on an ultra-high-speed fractional- ${ N}$ frequency divider and a highly linear phase-frequency detector (PFD). All circuits are integrated into a high-frequency SiGe bipolar technology. The programmable frequency divider can be operated at input frequencies between dc and 57 GHz for division factors in the entire integer range from 12 to 259. The PFD is optimized for fractional- ${ N}$ synthesis, which requires an extremely linear characteristic due to the modulation of its input frequency. The frequency divider and the PFD are used together with an 80-GHz wideband voltage-controlled oscillator (VCO) and transceiver for a high precision mm-wave frequency-modulated continuous-wave (FMCW) radar sensor. As shown by the experimental results the realized circuits stabilize the mm-wave VCO with an extremely low phase noise below $-{\hbox{97 dBc/Hz}}$ at 10-kHz offset around its center frequency of 80 GHz and can generate a highly linear frequency ramp with a bandwidth of 24 GHz. Furthermore, the accuracy of the synthesizer is demonstrated by FMCW radar distance measurements inside a waveguide and in free space. Inside the waveguide a standard deviation of the phase of the target below 0.0018 $^{\circ }$ (which corresponds to 9.4 nm) was measured.
69 citations
TL;DR: This work presents a sub-μW on-chip oscillator for fully integrated system-on-chip designs that introduces a resistive frequency locked loop topology for accurate clock generation and eliminates the traditional comparator from the oscillation loop.
Abstract: This work presents a sub- $\mu \text {W}$ on-chip oscillator for fully integrated system-on-chip designs. The proposed oscillator introduces a resistive frequency locked loop topology for accurate clock generation. In this topology, a switched-capacitor circuit is controlled by an internal voltage-controlled oscillator (VCO), and the equivalent resistance of this switched-capacitor is matched to a temperature-compensated on-chip resistor using an ultra-low power amplifier. This design yields a temperature-compensated frequency from the internal VCO. The approach eliminates the traditional comparator from the oscillation loop; this comparator typically consumes a significant portion of the total oscillator power and limits temperature stability in conventional RC relaxation oscillators due to its temperature-dependent delay. A test chip is fabricated in $0.18~\mu \text {m}$ CMOS that exhibits a temperature coefficient of 34.3 ppm/°C with long-term stability of less than 7 ppm (12 second integration time) while consuming 110 nW at 70.4 kHz. A radio transmitter circuit that uses the proposed oscillator as a baseband timing source is also presented to demonstrate a system-on-chip design using this oscillator.
59 citations
TL;DR: In this article, the authors demonstrate implementation of a phase-locked loop using a spin torque oscillator (STO) as a voltage controlled oscillator that generates a 7.344 GHz microwave signal stabilized by a 153 MHz reference signal.
Abstract: Spin torque oscillator (STO) has been attracting a great deal of attention as a candidate for the next generation microwave signal sources for various modern electronics systems since its advent. However, the phase noise of STOs under free running oscillation is still too large to be used in practical microwave applications, thus an industrially viable means to stabilize its oscillation has been strongly sought. Here we demonstrate implementation of a phase locked loop using a STO as a voltage controlled oscillator (VCO) that generates a 7.344 GHz microwave signal stabilized by a 153 MHz reference signal. Spectrum measurement showed successful phase locking of the microwave signal to the reference signal, characterized by an extremely narrow oscillation peak with a linewidth of less than the measurement limit of 1 Hz. This demonstration should be a major breakthrough toward various practical applications of STOs.
56 citations
TL;DR: This work presents the analysis and compares the performance of fundamental-mode voltage-controlled oscillators to harmonic-mode VCOs and proposes an H-VCO architecture, denoted as self-mixing VCO (SMV), where the VCO core generates both the first and second harmonic and then mixes them together to obtain the desired mm-wave third-harmonic.
Abstract: Frequency synthesis at mm-wave range suffers from a severe tradeoff between phase noise (PN) and frequency tuning range (FTR). This work presents the analysis and compares the performance of fundamental-mode voltage-controlled oscillators (F-VCOs) to harmonic-mode VCOs (H-VCOs). It is shown that unlike a mm-wave F-VCO, an H-VCO can simultaneously achieve higher FTR and lower PN. An H-VCO architecture, denoted as self-mixing VCO (SMV), is presented where the VCO core generates both the first $(f_0) $ and second harmonic $(2f_0) $ and then mixes them together to obtain the desired mm-wave third-harmonic $(3f_0)$ . Use of a Class-C push–push topology as the VCO core enhances the second-harmonic content to improve mixing efficiency, decreases parasitic capacitance, and improves PN. Compared to an F-VCO operating in a mm-wave band at a fundamental frequency that equals $3f_0$ , the proposed SMV architecture achieves about $2\times$ higher FTR and a better PN performance. A 52.8–62.5 GHz SMV prototype is designed and implemented in a $0.13\;\upmu \text{m}$ CMOS process. Measurement results show that the VCO achieves an FTR of 16.8% with a PN of $-100.6\text{ dBc/Hz}$ at 1 MHz offset—resulting in an FTR-inclusive figure-of-merit ( $\text{FoM}_\text{T}$ ) of $-190.85\text{ dBc/Hz} $ while consuming 7.6 mW from a 1.2 V supply.
53 citations
TL;DR: A very simple ring-oscillator voltage-controlled oscillator (VCO) structure for use in VCO-ADC applications is presented and has a greatly improved linearity compared with previously published VCOs.
Abstract: A very simple ring-oscillator voltage-controlled oscillator (VCO) structure for use in VCO-ADC applications is presented. It has a greatly improved linearity compared with previously published VCOs. Measurement results of a 1 V, 65 nm CMOS prototype confirm the effectiveness of the proposed approach.
25 Feb 2016
TL;DR: This work presents a new 28nm CMOS digital frac-N sampling PLL design that achieved 0.16ps rms jitter with 8.2mW and a state-of-the-art frack-N PLL FOM of -246.8dB.
Abstract: High-performance phase-locked-loops (PLLs) are key building blocks for many modern ICs. The sub-sampling PLL proposed in [1] uses a reference clock REF to sample a high-frequency VCO and converts phase/timing error into voltage. The steep dv/dt slope of the VCO helps to realize a high phase-detection gain and greatly suppresses the noise of loop components succeeding the phase detector, leading to low in-band phase noise and good PLL Figure-Of-Merit (FOM). However, the original design in [1] is analog and limited to integer-N (int-N) operation. It is desirable to extend it to more versatile fractional-N (frac-N) mode, and to make it digital for greater flexibility and more advanced digital calibration. This work presents a new 28nm CMOS digital frac-N sampling PLL design that achieved 0.16ps rms jitter with 8.2mW and a state-of-the-art frac-N PLL FOM of −246.8dB.
TL;DR: The paper provides an overview of the mechanisms that contribute to performance degradation in DTC-based PLL/phase modulators and presents ways to mitigate them and demonstrates state-of-the-art performance in nanoscale CMOS for fractional-N synthesis and phase modulation.
Abstract: We present an analog subsampling PLL based on a digital-to-time converter (DTC), which operates with almost no performance gap (176/198 fs RMS jitter) between the integer and the worst case fractional operation, achieving −246.6 dB FOM in the worst case fractional mode. The PLL is capable of two-point, 10 Mbit/s GMSK modulation with −40.5 dB EVM around a 10.24 GHz fractional carrier. The analog nonidealities—DTC gain, DTC nonlinearity, modulating VCO bank gain, and nonlinearity—are calibrated in the background while the system operates normally. This results in ~15 dB fractional spur improvement (from −41 dBc to −56.5 dBc) during synthesis and ~15 dB EVM improvement (from −25 dB to −40.5 dB) during modulation. The paper provides an overview of the mechanisms that contribute to performance degradation in DTC-based PLL/phase modulators and presents ways to mitigate them. We demonstrate state-of-the-art performance in nanoscale CMOS for fractional-N synthesis and phase modulation.
TL;DR: In this article, the authors focused on the noise elimination at a selected frequency from the line voltage of a two-level three-phase inverter, when it is driven by random space-vector pulsewidth modulation.
Abstract: This study has focused on the noise elimination at a selected frequency from the line voltage of a two-level three-phase inverter, when it is driven by random space-vector pulse-width modulation. Distribution of noise power in a wide range of frequencies in the conventional random pulse-width modulation (RPWM) methods may cause system resonant frequency excitation. Therefore, it can increase the acoustic noise and vibration in loads of inverters, especially ac motors. Thus, for the effective utilization of RPWM techniques, it is necessary to cancel noise at a specified frequency. The proposed method is able to create a gap in the spectrum of the line voltage at a selective frequency in the human hearing range. Therefore, unlike conventional RPWM techniques, switching periods are determined based on the position of the rotary reference vector. The presented relation between switching periods and the reference vector is used for the conventional space-vector pulse-width modulation (SVPWM) and two-phase SVPWM. The simulation and experimental results confirm that the proposed method effectively creates a gap at the selected frequency in power spectrum density of the line voltage of the three-phase inverter using random SVPWM.
03 Mar 2016
TL;DR: In this paper, the authors focus on the analysis and design of a current starved voltage controlled ring oscillator and analyze the effect of delay time, phase noise, layout area, and technology on the frequency of oscillation at various power supplies and control voltages.
Abstract: This paper focuses on and analysis and design of current starved voltage controlled ring oscillator. The analysis includes effect of delay time, phase noise, layout area, technology etc. on the frequency of oscillation at various power supplies and control voltages. The simulation results shows that the circuit has higher tuning range and low power consumption suitable for various application domains. Added benefit of this VCO is to maintain a constant amplitude level and oscillation. It is also proved here that the frequency of oscillation is inverse of the supply voltage and therefore consuming less power.
TL;DR: A triple-band (TB) oscillator was implemented in the TSMC 0.18 ㎛ 1P6M CMOS process, and it uses a cross-coupled nMOS pair and two shunt 4th order LC resonators to form a 6 th order resonator with three resonant frequencies.
Abstract: A triple-band (TB) oscillator was implemented in the TSMC 0.18 ㎛ 1P6M CMOS process, and it uses a cross-coupled nMOS pair and two shunt 4 th order LC resonators to form a 6 th order resonator with three resonant frequencies. The oscillator uses the varactors for band switching and frequency tuning. The core current and power consumption of the high (middle, low)- band core oscillator are 3.59(3.42, 3.4) ㎃ and 2.4(2.29, 2.28) ㎽, respectively at the dc drain-source bias of 0.67V. The oscillator can generate differential signals in the frequency range of 8.04-8.68 ㎓, 5.82-6.15 ㎓, and 3.68-4.08 ㎓. The die area of the triple-band oscillator is 0.835 × 1.103 ㎟.
IMEC1
TL;DR: The 57-to-66GHz TRX IC presented in this paper, whose architecture is depicted in Fig. 13.5.1, uses direct conversion and analog baseband beamforming, which is inherently simpler than superheterodyne and does not have to cope with the image frequency.
Abstract: Millimeter-Wave transceivers with beamforming capabilities, such as the one presented in this work, are a key technology to reach 4 or 6Gb/s at 10m range with the IEEE 802.11ad standard. Moreover, for mm-Wave access in 5G it will also be necessary to boost peak data-rates far beyond 1Gb/s at hundreds of meters in small cells. Transceiver architectures with beamforming often combine superheterodyne with RF beamforming [1], leading to a high power consumption and a suboptimal RX noise figure due to losses in the beamforming circuitry. In contrast, the 57-to-66GHz TRX IC presented in this paper, whose architecture is depicted in Fig. 13.5.1, uses direct conversion and analog baseband beamforming. Direct-conversion radios are inherently simpler than superheterodyne and do not have to cope with the image frequency, but on the other hand they may suffer from pulling of the PA on the VCO. In this work this is avoided by the non-integer ratio of 2.5 between the operating frequency and the 24GHz PLL that subharmonically injection locks a 60GHz quadrature oscillator (Fig. 13.5.2).
TL;DR: A switched-transformer VCO (ST-VCO) based on dual-band topology is proposed to increase the frequency tuning range and transformer-distribution ILFDs (TD-ILFDs) are demonstrated to achieve much improved frequency locking range with compact chip area and low power consumption.
Abstract: Several transformer-based techniques are proposed to enhance the frequency tuning range of mm-wave voltage-controlled oscillators (VCOs) and the frequency locking range of injection-locked frequency dividers (ILFDs). Firstly, a switched-transformer VCO (ST-VCO) based on dual-band topology is proposed to increase the frequency tuning range. Secondly, transformer-distribution ILFDs (TD-ILFDs) are demonstrated to achieve much improved frequency locking range with compact chip area and low power consumption. Thirdly, the injection-saturation problem of ILFDs is identified, analyzed, and solved in this work. A VCO and three different TD-ILFDs are designed and fabricated in a 65 nm CMOS process. The proposed ST-VCO measures wide tuning range of 22.3% from 62.1 GHz to 78.3 GHz with phase noise of −112 dBc/Hz at 10 MHz offset while consuming 7.7 mW, corresponding to FoM and FoMT of −180.4 dBc/Hz and −187.4 dBc/Hz, respectively. The proposed 60-GHz TD-ILFDs measure locking range of 19.6 GHz (29.6%), 19.8 GHz (29.2%), and 3.8 GHz (6.1%) while consuming 1.44 mW, 1.44 mW, and 0.44 mW.
TL;DR: In this article, a CMOS LC voltage-controlled oscillator capable of covering both the Ku and Ka bands is presented, where a PMOS push-push frequency doubler, together with the inductor of the low-band LC VCO, is adopted to boost the low Ku-band toward high Ka-band.
Abstract: A CMOS LC voltage-controlled oscillator (VCO) capable of covering both the Ku and Ka bands is presented. The Ku-band frequency source is generated from a low-noise cross-coupled LC VCO. A PMOS push-push frequency doubler, together with the inductor of the low-band LC VCO, is adopted to boost the low Ku-band toward high Ka-band. This proposed VCO is implemented in a standard 0.18 $\mu\text{m}$ CMOS with 1.35 V supply voltage. The dual-band VCO consumes a small active area of 0.49 mm $\times$ 0.2 mm and low DC power of 3 mW at both bands. At 1 MHz (10 MHz) offset, the measured output phase noises are −109.30 dBc/Hz (−130.54 dBc/Hz) at 15.126 GHz and −102.33 dBc/Hz (−124.10 dBc/Hz) at 30.251 GHz.
TL;DR: A low-jitter and fractional-resolution injection-locked clock multiplier (ILCM) with a delay-locked-loop (DLL)-based process-voltage-temperature (PVT)-calibrator is proposed, which can overcome real-time frequency drifts as well as static process variations.
Abstract: A low-jitter and fractional-resolution injection-locked clock multiplier (ILCM) with a delay-locked-loop (DLL)-based process-voltage-temperature (PVT)-calibrator is proposed. The ring-type voltage-controlled oscillator (VCO) and the voltage-controlled delay line (VCDL) of the DLL consist of identical delay cells, and they share the same control voltage. Thus, by changing the ratio between the numbers of stages of the VCDL and the VCO, the frequency of the VCO can be calibrated at any target frequencies, noninteger times the reference frequency. As the amount of the unit delay is adjusted continuously by the DLL, the VCO can overcome real-time frequency drifts as well as static process variations; thus, excellent jitter performance can be sustained during any environmental variations. The proposed ILCM, designed in the 65 nm CMOS process, generated output frequencies that range from 1.2 to 2.0 GHz with a frequency resolution of 40 MHz and a 400 MHz reference clock. When injection locked, the integrated jitter from 1 kHz to 40 MHz of the 1.6 GHz signal was 440 fs. The proposed real-time PVT calibrator restricted the degradations of phase noise and jitter over the temperature and the supply variations to less than 0.7 dB and 20%, respectively. The active area was ${0}.{032}\;\text{m}{\text{m}^{2}}$ and the power consumption was 3.6 mW.
TL;DR: The design, analysis, computer simulation, and experimental measurement of fractional-order sinusoidal oscillator with two current conveyors, two resistors, and two fractional immittance elements confirm the attractive features of the proposed oscillator.
Abstract: This paper deals with the design, analysis, computer simulation, and experimental measurement of fractional-order sinusoidal oscillator with two current conveyors, two resistors, and two fractional immittance elements. The used conveyor is based on the bulk-driven quasi-floating-gate technique in order to offer high threshold-to-supply voltage ratio and maximum input-to-supply voltage ratio. The supply voltage of the oscillator is 1 V, and the power consumption is $$74\,\upmu \hbox {W}$$74μW, and hence the proposed oscillator can be suitable for biomedical, portable, battery-powered, and other applications where the low-power consumption is critical. A number of equations along with graphs describing the theoretical properties of the oscillator are presented. The unique features of fractional-order oscillator are highlighted considering practical utilization, element computation, tuning, phase shift of output signals, sensitivities, etc. The simulations performed in the Cadence environment and the measurements of a real chip confirm the attractive features of the proposed oscillator.
22 May 2016
TL;DR: In this article, a resonant-tunneling-diode (RTD) terahertz oscillator with a large modulation bandwidth was fabricated, and wireless communication using 500 GHz range was demonstrated.
Abstract: A resonant-tunneling-diode (RTD) terahertz oscillator with a large modulation bandwidth was fabricated, and wireless communication using 500 GHz range was demonstrated. The RTD oscillator was directly modulated using a pulse pattern generator. Although the bit error rate (BER) degraded with the bit rate owing to the increase in losses of the cable and bias tee with frequency, a very high bit rate of 30 Gbps with a correctable BER of 1.3 × 10−3 was achieved.
TL;DR: In this paper, a new technique to design and analyze a multi-phase oscillator is proposed based on the fractional-order elements or constant phase elements in order to generate equal or different phase shifts.
Abstract: Recently, multi-phase oscillator design witnesses a lot of progress in communication especially phase shift keying based systems. Yet, there is a lack in design multi-phase oscillator with different fractional phase shifts. Thus, in this paper, a new technique to design and analyze a multi-phase oscillator is proposed. The proposed procedure is built based on the fractional-order elements or constant phase elements in order to generate equal or different phase shifts. The general characteristics equation for any oscillator is studied to derive expressions for the oscillation conditions and oscillation frequency. Also, stability analysis is introduced to guarantee the oscillation. Then, different examples of oscillators for equal and different phase shifts are introduced with their simulations.
25 Feb 2016
TL;DR: An injection-locked clock multiplier (ILCM) is considered to be a promising solution that can generate low-jitter, high-frequency clocks, using a limited budget in terms of silicon area and power consumption, but its jitter performance is sensitive to process, voltage, and temperature (PVT) variations.
Abstract: An injection-locked clock multiplier (ILCM) is considered to be a promising solution that can generate low-jitter, high-frequency clocks, using a limited budget in terms of silicon area and power consumption. However, an ILCM has a critical problem in that its jitter performance is sensitive to process, voltage, and temperature (PVT) variations. Thus, in general, an ILCM must be equipped with a dedicated PVT-calibrator to mitigate the sensitivity of its performance to PVT variations. One of the most general calibration methods is to use a phase-locked loop (PLL). This method can correct static frequency deviations of a voltage-controlled oscillator (VCO) due to process variations, but it cannot prevent real-time frequency drifts due to temperature or voltage variations [1]. Recently, many efforts have been made to develop new PVT-calibrators, capable of continuous frequency tracking [1–6]. In [1–3], frequency drifts were monitored by a replica-VCO or a delay-locked loop (DLL) that used the same delay cells as the main VCO. However, in these architectures, each calibrator must spend the same amount of the power as the VCO. In addition, mismatches between delay cells limit the calibrating precision or demand an additional calibrating step. References [4–6] presented frequency-tracking loops (FTLs) based on various methods to detect the phase shifts of VCO outputs when reference-pulses are injected. Reference [4] used a time-to-digital converter (TDC) to detect the phase shifts, but it had large power consumption and silicon area due to the many digital circuits. Although the FTL of [5] used a timing-adjusted phase detector (PD), it could suffer from large in-band noise or spurs since the switches of the charge pump (CP) must be on for a considerable duration in every period. In [6], a pulse-gating technique that periodically skipped the injection was presented, but it could generate fractional spurs.
TL;DR: In this paper, a proximity coupling RF sensor based on injection-locked phase-locked loop (PLL) for wrist pulse detection is proposed, which is composed of two main parts: a free-running oscillator and a PLL synthesizer containing a voltage-controlled oscillator.
Abstract: In this paper, a proximity coupling RF sensor based on injection-locked phase-locked loop (PLL) for wrist pulse detection is proposed. The sensor is composed of two main parts: a free-running oscillator and a PLL synthesizer containing a voltage-controlled oscillator. The free-running oscillator is built with a two-port microstrip line resonator (inter-digital electrodes), which acts as part of a transducer that can transform the expansion or contraction of the radial artery into an impedance variation. Measurements show that the impedance variation of the resonator due to changes in the radial artery causes a frequency change of up to 0.74 MHz in the free-running oscillator. For the PLL part, the frequency change can be transformed to a variation in dc voltage by injection of the modulated signal from the wrist pulse into a phase-locked oscillator. The variation of the loop-control voltage, in one cycle of the pulse, is approximately 10–15 mV peak-to-peak. Our sensor is demonstrated to be an effective noncontact and noninvasive scheme for wrist pulse detection.
TL;DR: In this paper, a transformer-coupled QVCO topology with extra phase shift is proposed to replace the coupling transistors, which eliminates coupling transistor's noise, decouples the tradeoff between PN and phase error, and improves the PN performance.
Abstract: This paper presents new circuit topologies and design techniques for low-phase-noise (PN) complementary metal–oxide–semiconductor (CMOS) millimeter-wave quadrature voltage-controlled oscillator (QVCO) and VCOs. A transformer-coupled QVCO topology with extra phase shift is proposed to replace the coupling transistors, which eliminates coupling transistors’ noise, decouples the tradeoff between PN and phase error, and improves the PN performance. This technique is demonstrated in a millimeter-wave QVCO with a measured PN of −119.2 dBc/Hz at 10-MHz offset of a 56.2-GHz carrier and a tuning range of 9.1%. In addition, an inductive-divider-feedback technique is proposed in an $LC$ VCO design to improve the transconductance linearity, resulting in a larger signal swing and lower PN compared with the conventional $LC$ VCOs. The effectiveness of this approach is demonstrated in a 76- and a 90-GHz VCO design, both fabricated in a 65-nm CMOS process, with an FOM $_{{\mathrm {T}}}$ of 173.6 and 173.1 dBc/Hz, respectively.
TL;DR: A wideband and low phase noise quadrature local oscillation (LO) signal generator for multistandard cellular transceivers was proposed, and the required frequency-tuning range (FTR) of a voltage-controlled oscillator (VCO) was reduced to 39%, which can be easily covered by a single LC-VCO.
Abstract: A wideband and low phase noise quadrature local oscillation (LO) signal generator for multistandard cellular transceivers was proposed. Using the new LO-plan consisting of divide-by-6, divide-by-4, and divide-by-12 frequency dividers, the required frequency-tuning range (FTR) of a voltage-controlled oscillator (VCO) was reduced to 39%, which can be easily covered by a single LC -VCO. Due to the reduced FTR, the VCO can retain a high Q -factor and achieve low phase noise. The key building block of the new LO-plan is a quadrature divide-by-6 divider, capable of generating precise I / Q signals. To implement the quadrature divide-by-6 divider, we proposed a fully differential divide-by-3 divider with 50% duty cycle. Using the same idea, a fully differential divide-by-2 circuit was also proposed for divide-by-4 and divide-by-12 dividers. The proposed LO-generator was fabricated in a 40 nm CMOS process, and covered LO-frequencies of 0.56–2.92 GHz for multistandard cellular transceivers. The LO-generator occupied a small silicon area of $0.15\;\text{mm}^{2}$ and achieved an excellent phase noise performance of $- {141}.{02}\;\text{dBc}/\text{Hz}$ at a 1 MHz offset from a 709 MHz LO-frequency.
TL;DR: In this article, a low-power low-phase-noise VCO with self-adjustable active resistor (SAAR) is presented, where a pair of PMOS transistors is introduced between cross-coupled pairs and LC-tank, serving as the SAAR.
Abstract: This letter presents a low-power low-phase-noise VCO with self-adjusted active resistor (SAAR). A pair of PMOS transistors is introduced between cross-coupled pairs and LC-tank, serving as the SAAR. When cross-coupled transistor resides in the saturation region, SAAR exhibits small resistance, enabling fast switching and suppressing flicker noise up-conversion to $1/f^{3}$ phase noise. Moreover, as cross-coupled transistor enters triode region, SAAR will adjust to larger resistance and prevent the small conducting resistance of the cross-coupled transistor degrading the quality factor of LC tank. Fabricated in a 65 nm CMOS technology, the proposed VCO demonstrates a tuning range of 5.07–6.35 GHz (22.4%) with only 0.42 mW power consumption at 0.6 V supply. The phase noise in the worst case is $-$ 40.8 dBc/Hz at 1 kHz and $-$ 111 dBc/Hz at 1 MHz, respectively.
TL;DR: In this paper, a resonant tunnelling diode terahertz voltage-controlled oscillator integrated with a varactor diode (RTD VCO) for a wide tuning range was proposed and fabricated.
Abstract: A resonant tunnelling diode terahertz voltage-controlled oscillator integrated with a varactor diode (RTD VCO) for a wide tuning range was proposed and fabricated. In single RTD VCO, a tuning range of 120 GHz of the centre frequency of 640 GHz was achieved by a good combination of the RTD and varactor capacitances. A multi-element array of RTD VCOs was fabricated to increase the tuning range. A very wide frequency tuning of 320 GHz (580–900 GHz) was achieved with a four-element RTD VCO array.
TL;DR: A SiGe signal generator MMIC was developed that achieves 28.7 dBm peak output power with 21.9% PAE and over 27.4 dBm of output power over the whole frequency range from 19.7 GHz to 28.2 GHz.
Abstract: High-frequency systems such as mm-wave radar transmitters and LO/RF driver chains in vector network analyzers (VNAs) often require the generation of signals with high output power. While these systems benefit considerably from the reduction in size and cost provided by SiGe integration, their output power must be further increased in order to meet the performance of other technologies (e.g., GaAs). To this end, a SiGe signal generator MMIC was developed that achieves 28.7 dBm peak output power with 21.9% PAE and over 27.4 dBm of output power over the whole frequency range from 19.7 GHz to 28.2 GHz. The output power is scalable with DC current up to a maximum of 30.8 dBm. The signal generator is based on a VCO, power amplifier cells (PA cells) and lumped-element Wilkinson power combiners/dividers. The VCO’s phase noise is less than −96 dBc/Hz at 1 MHz offset over the entire frequency range. The developed single PA cell achieves a maximum saturated output power $P_{\mathrm {sat}}$ of 24.7 dBm with peak PAE of 31%. This article describes the design and performance of all components. The signal generator MMIC has been integrated in an evaluation board together with a PLL, power supply, and serial interface.