Showing papers on "Voltage-controlled oscillator published in 2020"

A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/ f Noise Upconversion Caused by Short-Channel Effects

Abstract: Class-C operation is leveraged to implement a $K$ -band CMOS voltage-controlled oscillator (VCO) where the upconversion of $1/f$ current noise from the cross-coupled transistors in the oscillator core is robustly contained at a very low level. Implemented in a bulk 28-nm CMOS technology, the 12%-tuning-range VCO shows a phase noise as low as −112 dBc/Hz at 1-MHz offset (−86 dBc/Hz at 100 kHz offset) from a 19.5 GHz carrier while consuming 20.7 mW, achieving a figure of merit (FoM) of −185 dBc/Hz. The design is complemented by a theoretical investigation of $1/f$ noise upconversion caused by short-channel effects in the cross-coupled transistors, obtaining the first instance of a closed-form phase noise expression in the $1/f^{3}$ region.

An mm-Wave Synthesizer With Robust Locking Reference-Sampling PLL and Wide-Range Injection-Locked VCO

Abstract: In this article, a two-stage millimeter (mm)-wave frequency synthesizer with low in-band noise and robust locking reference-sampling techniques is presented. Using a two-stage scheme allows separately dealing with the low phase noise (PN) frequency synthesis in the first stage and the mm-wave frequency multiplication in the second stage, achieving the best overall power efficiency. In the first stage, a voltage domain reference-sampling phase detector (RSPD)-locked loop (RSPLL) is adopted to achieve both low PN and robust locking without additional frequency locking loop. A reference reshaping buffer is implemented to improve the phase detector gain and in-band PN. The reference rising/falling time is programmable to achieve optimal RSPLL performance even under external disturbances. The second stage employs an injection-locked voltage-controlled oscillator (ILVCO) for 4 $\times $ frequency multiplication. A low-power digital frequency tracking loop (FTL) detecting actual frequency errors is implemented in order to achieve wide operation range for the ILVCO while using a high ${Q}$ tank with low power. The prototype synthesizer was fabricated in a 45-nm partially depleted silicon on insulator (PDSOI) CMOS technology. The first stage 9-GHz RSPLL achieves 144-fs integrated jitter with 7.2-mW power consumption, achieving a figure of merit (FoM) of −248 dB and the overall mm-wave synthesizer achieves 251-fs integrated jitter with 20.6-mW power consumption at 35.84 GHz, achieving an FoM of −238.9 dB.

A 6.5- μ W 10-kHz BW 80.4-dB SNDR G m -C-Based CT ∆∑ Modulator With a Feedback-Assisted G m Linearization for Artifact-Tolerant Neural Recording

Abstract: This article presents a Gm-C-based continuous-time delta–sigma modulator (CTDSM) for artifact-tolerant neural recording interfaces. We propose the feedback-assisted Gm linearization technique, which is applied to the first Gm-C integrator by using a resistive feedback digital-to-analog converter (DAC) in parallel to the degeneration resistor of the input Gm. This enables the input Gm to process the quantization noise, thereby improving the input range and linearity of the Gm-C-based CTDSM, significantly. An energy-efficient second-order loop filter is realized by using a voltage-controlled oscillator (VCO) as the second integrator and a phase quantizer. A proportional–integral (PI) transfer function is employed at the first integrator, which minimizes the output swing while maintaining loop stability. Fabricated in a 110-nm CMOS process, the prototype CTDSM achieves a high input impedance, 300-mVpp linear input range, 80.4-dB signal-to-noise and distortion ratio (SNDR), 81-dB dynamic range (DR), and 76-dB common-mode rejection ratio (CMRR) and consumes only 6.5 $\mu \text{W}$ with a signal bandwidth of 10 kHz. This corresponds to a figure of merit (FoM) of 172.3 dB, which is the state of the art among the neural recording ADCs. This work is also validated through the in vivo experiment.

A Coarse-Fine VCO-ADC for MEMS Microphones With Sampling Synchronization by Data Scrambling

Abstract: This letter presents a mostly digital analog-to-digital converter implemented with voltage-controlled oscillators that can directly interface a capacitive MEMS microphone. The ADC is based on two ring oscillators and a coarse-fine counting circuitry. Coarse and fine counters are synchronized using a novel data scrambling technique to mitigate metastability and timing errors. This method enables a very low power consumption in the digital post-processing circuit. The proposed ADC, prototyped in 130-nm CMOS, achieves 73.8 dB-A of signal-to-noise and distortion ratio (SNDR) peak and 97 dB of dynamic range (DR) in a 20-kHz BW, while consuming 240 $\mu \text{W}$ from the 1.5-V/1.2-V power supplies. In a reduced power mode (8 kHz BW) with relaxed oscillation parameters, it reaches 66.4 dB-A of SNDR peak and 93 dB of DR with a power consumption of only 77 $\mu \text{W}$ .

Versatile Dual-Receiver 94-GHz FMCW Radar System With High Output Power and 26-GHz Tuning Range for High Distance Applications

Abstract: Airborne applications demand exceptional overall radar system performance and eminently high output power for high range target detection. The frequency modulated continuous wave (FMCW) radar system presented in this article is capable of achieving this task due to its high output power at 94-GHz center frequency with over 26-GHz tuning range. Nevertheless, the radar still provides a small form factor and low power consumption of 4.25 W at 5 V single Universal Serial Bus (USB) supply. The key system component is a Silicon Germanium (SiGe) bipolar complementary metal-oxide-semiconductor (BiCMOS) monolithic microwave integrated circuit (MMIC) that contains a 94-GHz voltage-controlled oscillator (VCO), and a 27-GHz VCO for dual-loop phase-locked loop (PLL) stabilization, a power amplifier (PA), and two receive mixers. It generates frequency ramps between 83- and 109-GHz with a maximum output power of 19.7 dBm at its output after the bond wires on the printed circuit board (PCB) and 14.8-dBm output power at the radar’s transmit (TX)-waveguide WR-10-flange. The sensor was also tested in a temperature range from −40 °C to +70 °C with menial deviation. Thus, the system offers high system dynamic range and far distance target detection range. Following a detailed system description, we finally present the FMCW range and Doppler measurements performed with the presented radar sensor as well as the application on unmanned aerial vehicles (UAVs) for flight altitude control and as airborne collision avoidance system (ACAS).

A 3.3-mW 25.2-to-29.4-GHz Current-Reuse VCO Using a Single-Turn Multi-Tap Inductor and Differential-Only Switched-Capacitor Arrays With a 187.6-dBc/Hz FOM

Abstract: A millimeter-wave current-reuse voltage-controlled oscillator (VCO) features a single-turn multi-tap inductor and two separate differential-only switched-capacitor arrays to improve the power efficiency and phase noise (PN). Specifically, a single-branch complementary VCO topology, in conjunction with a multi-resonant Resistor-Inductor-Capacitor-Mutual inductance (RLCM) tank, allows sharing the bias current and reshaping the impulse-sensitivity-function. The latter is based on an area- efficient RLCM tank to concurrently generate two high quality- factor differential-mode resonances at the fundamental and 2nd- harmonic oscillation frequencies. Fabricated in 65-nm CMOS technology, our VCO at 27.7 GHz shows a PN of −109.91-dBc/Hz at 1-MHz offset (after on-chip divider-by-2), while consuming just 3.3 mW at a 1.1-V supply. It corresponds to a Figure-of-Merit (FOM) of 187.6 dBc/Hz. The frequency tuning range is 15.3% (25.2 to 29.4 GHz) and the core area is 0.116 mm2.

A 2.65-pJ/Bit 12.5-Gb/s 60-GHz OOK CMOS Transmitter and Receiver for Proximity Communications

Abstract: This article presents a high data rate, high-efficiency 60-GHz on–off keying (OOK) CMOS transmitter and receiver. The transmitter consists of a voltage-controlled oscillator (VCO) and a modulator. The receiver consists of a low-noise amplifier, detector, and limiting amplifier (LA) and has a compact design. An analysis of the on–off isolation of the modulator and bandwidth of the LA reveals that the proposed transformer (TF) between the modulator and the VCO can improve the on–off isolation, and the feedforward capacitor can enhance the bandwidth. Implemented in the 65-nm CMOS technology, the transmitter and the receiver consume dc powers of 12.1 and 21 mW, respectively, at 12.5 Gb/s. Moreover, they occupy core chip areas of 0.09 and 0.06 mm2, respectively. The transceiver system is constructed with on-board Yagi–Uda antennas, and it achieves 12.5 Gb/s wireless OOK data transmission for a pseudorandom binary sequence of length 27 −1 with a bit error rate of less than 10−12. The proposed transceiver system achieves an energy efficiency of 2.65 pJ/bit.

Design of a 100-GHz Double-Sideband Low-IF CW Doppler Radar Transceiver for Micrometer Mechanical Vibration and Vital Sign Detection

Abstract: This article presents a fully integrated 100-GHz continuous-wave Doppler radar transceiver with the double-sideband low-intermediate-frequency (IF) architecture for mechanical vibration and vital sign detection. Fabricated in a 65-nm CMOS process, the whole radar chip transceiver consumes 262 mW with a size of 0.9 mm $\times2.0$ mm. Instead of utilizing a fundamental 100-GHz voltage controlled oscillator (VCO) in the chip, a push–push frequency doubler with the 50-GHz external source is adopted to drive the transceiver. Under a dedicated design on the system architecture and circuit blocks, the chip could transmit 4-dBm saturated power ( $P_{\mathrm {sat}}$ ) over 93–105 GHz with a 40-mV 1-kHz IF carrier and achieve good I/Q performance of phase mismatch $\mu \text{m}$ displacement from 1.5 m, the human vital-sign signal from 2 m, and even a small bullfrog’s hybrid respiratory motion from 0.6 m. To the best of our knowledge, this is the first 100-GHz CMOS Doppler radar transceiver chip with the low-IF architecture for the biological vital sign detection.

An X-Band GaN HEMT Oscillator with Four-Path Inductors

Abstract: An X-band GaN HEMT oscillator implemented with the WIN 0.25 μm GaN HEMT technology is proposed. The oscillator consists of a HEMT amplifier with an LC feedback network with four-path inductors. With the supply voltage of VDD = 2 V, the GaN VCO current and power consumption of the oscillator are 10.8 mA and 21.6mW, respectively. The oscillator can generate single-ended signal at 8.82 GHz and it also supplies output power 1.24 dBm. At 1MHz frequency offset from the carrier the phase noise is 124.95 dBc/Hz. The die area of the GaN HEMT oscillator is 2×1 mm2.

A 5-GS/s 7.2-ENOB Time-Interleaved VCO-Based ADC Achieving 30.5 fJ/cs

Abstract: This article presents an eight-channel time-interleaved voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC), achieving 7.2 effective number of bits (ENOBs) at 5 GS/s in 28-nm CMOS. A high-speed ring oscillator with feedforward cross-coupling and a shared tail transistor is combined with an asynchronous counter in order to improve the resolution while minimizing the power consumption. Asynchronous double sampling is used to enable reliable sampling of the asynchronous counter state. On-chip digital calibration is used to compensate for channel mismatch and nonlinear distortion, and sampling time mismatch is corrected using tunable clock delays. With a total power consumption of just 22.7 mW, it achieves a Walden figure-of-merit (FOM) of 30.5 fJ/cs.

Current/Voltage Controlled Quadrature Sinusoidal Oscillators for Phase Sensitive Detection Using Commercially Available IC.

Abstract: This paper presents the quadrature sinusoidal oscillators for a phase sensitive detection (PSD) system. The proposed oscillators are design by using the commercially available ICs (LT1228). The core oscillator consists of three LT1228s: two grounded capacitors and one resistor. By adding four resistors without the requirement of additional active devices, the amplitudes of two quadrature waveforms become adjustable. The quadrature output nodes are of low impedance, which can be connected to the impedance sensor or other circuits in a phase sensitive detection system without the need of buffer devices. The amplitudes of the quadrature waveform are equal during the frequency of oscillation (FO) tuning. The frequency of oscillation is electronically and linearly controlled by bias current or voltage without affecting the condition of oscillation (CO). Furthermore, the condition of oscillation is electronically controlled without affecting the frequency of oscillation. The performances of the proposed oscillators are experimentally tested with ±5 voltage power supplies. The frequency of the proposed sinusoidal oscillator can be tuned from 8.21 kHz to 1117.51 kHz. The relative frequency error is lower than 3.12% and the relative phase error is lower than 2.96%. The total harmonic distortion is lower than -38 dB (1.259%). The voltage gain of the quadrature waveforms can be tuned from 1.97 to 15.92. The measurement results demonstrate that the proposed oscillators work in a wide frequency range and it is a suitable choice for an instrument-off-the-shelf device.

17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and −250dB FoM

Abstract: Sub-sampling (SS) and injection-locking (IL) techniques are becoming increasingly popular for 5G millimeter-wave (mmW) frequency generation [1], [2] due to their ability to achieve ultra-low jitter (<100fs). However, as indicated in Fig. 17.6.1 (top-left), sub-sampling PLLs (SS-PLL) typically suffer from high-power consumption, especially in mmW VCO buffers, which isolate the VCO from its sampler for reducing reference spurs, and in the high-speed dividers [2]–[4]. Also, the analog loop filter usually occupies large area. On the other hand, the IL technique for mmW frequency generation requires power-hungry high-frequency injection (~GHz) to fully suppress the oscillator phase noise [1], [4] and cannot ensure robustness over PVT (process, voltage, temperature) [4], which requires an additional frequency-tracking loop (FTL), see Fig. 17.6.1 (top-right). Furthermore, there exists a significant danger of a timing-race problem between the injection reference and FTL, since the frequency error may be corrected by IL before the FTL senses it. In [1], the FTL based on a phase averaging technique can solve the timing-race problem but requires a QVCO and an analog loop filter with relatively large area.

A Voltage-Controlled Ring Oscillator With VCO-Gain Variation Compensation

Abstract: A voltage-controlled oscillator (VCO) with VCO-gain ( $K_{\mathrm {VCO}}$ ) variation compensation is proposed to reduce $K_{\mathrm {VCO}}$ variation in a current-mode logic (CML) ring oscillator by introducing a cross-coupled pair with capacitive degeneration that mitigates the nonlinearity of $K_{\mathrm {VCO}}$ . Designed and fabricated in a standard 0.18- $\mu \text{m}$ CMOS process, the proposed VCO can be tuned from 1.78 to 2.53 GHz, with the VCO gain variation less than 14.01%, while occupying a core area of $0.185\times0.081$ mm2 and consuming 20 mA including the bias circuitry, from a 1.8-V supply voltage. The phase noise is measured to be −92.68 dBc/Hz at 1 MHz offset and −114.97 dBc/Hz at 10 MHz offset from the high-band carrier frequency, respectively.

A 16.1-bit Resolution 0.064-mm 2 Compact Highly Digital Closed-Loop Single-VCO-Based 1-1 Sturdy-MASH Resistance-to-Digital Converter With High Robustness in 180-nm CMOS

Abstract: A novel direct resistive-sensor-to-digital readout circuit is presented, which achieves 16.1-bit ENOB while being very compact and robust. The highly digital time-based architecture employs a single voltage-controlled oscillator (VCO), counter, and digital feedback loop for the readout of an external single-ended highly nonlinear resistive sensor, such as an NTC thermistor. In addition to the inherent first-order noise shaping due to the oscillator, the second loop in SMASH configuration creates second-order noise shaping. Fabricated in 180-nm CMOS, the readout circuit achieves 16.1 bit of resolution for 1-ms conversion time and consumes only $171~\mu \text{W}$ , resulting in an excellent 2.4-pJ/c.s. FOMW for a resistive sensor interface while occupying only 0.064 mm 2. The specific closed-loop architecture tackles the VCO nonlinearity, achieving more than 14 bits of linearity. Multiple prototype chip samples have been measured in a temperature-controlled environment from −40 °C to 125 °C for the readout of commercial external NTC thermistors. A maximum temperature inaccuracy of 0.3 °C is achieved with only one-point trimming at room temperature. Since the circuit architecture decouples the sensor excitation from the feedback, high electromagnetic interference (EMI) immunity at the sensor node is demonstrated as well.

Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools

Abstract: Optimal voltage-controlled oscillator (VCO) design for ultralow-power (ULP) radios has to fulfill simultaneously multiple requirements such as frequency tuning range, phase noise, power consumption, and frequency pushing. The manual design struggles to approach the full potential that a given topology can achieve. In this work, we prove the role of electronic design automation (EDA) tools by fully supporting the complex design of a ULP complementary Class-B/C hybrid-mode VCO. In the 1st step of the EDA-assisted flow, we perform a worst-case corner of worst-case tuning sizing optimization over a 108-dimensional performance space, offering sizing solutions with power consumption down to $145~\mu \text{W}$ at the worst-case. In the 2nd step, we introduce an automatic layout generation tool to offer valuable insights into the post-layout design space and devise a ready-for-tape-out fine optimization strategy. The hybrid-mode VCO prototyped in 65-nm CMOS occupies a die area of 0.165 mm2 and dissipates $297~\mu \text{W}$ from a 0.8 V supply at 5.1 GHz. The phase noise at 1 MHz offset is −110.1 dBc/Hz, resulting in a competitive Figure-of-Merit (FoM) of 189.4 dBc/Hz well-suited for ULP applications.

Unified Analog PUF and TRNG Based on Current-Steering DAC and VCO

Abstract: This work presents a unified weak physical unclonable function (PUF) and a true random number generator (TRNG) based on the current-steering digital-to-analog converter (DAC) and ring voltage-controlled oscillator (VCO). Entropy source for the weak PUF is the mismatch between NMOS and PMOS transistors in a cascode current DAC as well as the mismatch between VCO quantizers, while entropy source for the TRNG is thermal noise in the DAC and VCO and clock jitter. Instead of using spatial entropy sources for the PUF, i.e., multiple unit PUF elements, the proposed architecture utilizes temporal entropy source by capturing the output of unit PUF element over multiple cycles, which reduces area significantly. A unified PUF/TRNG prototype is fabricated in 65-nm CMOS and consumes 0.36 pJ/bit at a throughput of 100 Mb/s. The PUF has a measured intra-HD of 0.0906 and inter-HD of 0.4859, while the raw TRNG bitstream has an entropy of 0.9991 and passes all the NIST statistical randomness tests.

Low Power Low Phase Noise 60 GHz Multichannel Transceiver in 28 nm CMOS for Radar Applications

Abstract: This paper presents a highly integrated 60 GHz transceiver for FMCW radar applications realized in a 28 nm bulk CMOS technology. The chip provides two transmit (TX) and three receive (RX) channels. The 60 GHz local oscillator (LO) distribution is fed with the frequency-multiplied signal of the integrated low phase noise 15 GHz voltage-controlled oscillator (VCO). Realized in 28 nm technology node, the proposed chip is able to generate chirp signals over a continuous 57–64 GHz frequency-tuning-range. The phase noise is <−93 dBc/Hz @ 1 MHz offset. The measured peak phase noise performance is −99 dBc/Hz @1 MHz offset for a 55.5 GHz carrier frequency. The single TX/RX DC power consumptions are 63 mW and 39 mW, respectively. The total DC power dissipation is 478 mW.

A Sub-mW 2.4-GHz Active-Mixer-Adopted Sub-Sampling PLL Achieving an FoM of −256 dB

Abstract: An active-mixer-adopted sub-sampling phase-locked loop (AMASS-PLL) is presented that replaces the passive-mixer-like sample-and-hold switches and charge pump (CP) of a sub-sampling PLL (SSPLL) with an active-mixer and $g_{m}$ -cell, which reduces spurious content by 20 dB while enabling sub-mW power consumption at 2.4 GHz. Specifically, an active-mixer-based phase detector is used to improve the isolation between the voltage-controlled oscillator (VCO) and the sampling mechanism, which helps to address the inherent problem of high reference spurs in SSPLLs. Fabricated in 65 nm, the AMASS-PLL achieves an rms jitter of 161 fs from 10 kHz to 100 MHz with a spur of −67 dBc, all at a power of 0.93 mW, for a figure of merit (FoM) of −256 dB.

A 65–81 GHz CMOS Dual-Mode VCO Using High Quality Factor Transformer-Based Inductors

Abstract: This paper presents a wide-tuning range dual-mode millimeter wave (mm-wave) voltage controlled oscillator (VCO) incorporating high quality-factor (Q) transformer-based variable inductors. A high Q switched inductor with two different values is proposed by constructing the load of a transformer of a high Q fixed capacitor in series with a lossless switch structure that does not add any loss to the LC-tank as implemented by changing the signals mode across the capacitor. By choosing a proper center frequency for each mode and sufficient frequency overlap, a wide frequency tuning range (FTR) mm-wave VCO can be designed. It provides almost twice higher tuning range while keeping phase noise (PN) nearly the same as the two-mode VCO designed with two standalone inductors. Fabricated in a 65 nm CMOS process, the VCO demonstrates the measured FTR of 22.8% from 64.88 to 81.6 GHz range. The measured peak PN at 10 MHz offset is -114.63 dBc/Hz and the maximum and minimum corresponding figures of merit FOM and FOM $_{\mathbf {T}}$ are -173.9 to -181.84 dB and -181.07 to -189 dB, respectively. The VCO cores consume 10.2 mA current from 1 V power supply, and the occupied area is $0.146\times 0.205$ mm $^{\mathbf {2}}$ .

A Very Low Phase-Noise Transformer-Coupled Oscillator and PLL for 5G Communications in 0.12 $\mu$ m SiGe BiCMOS

Abstract: This article presents a 9.9–12.45 GHz voltage-controlled oscillator (VCO) designed in 0.12 $\mu \text{m}$ SiGe BiCMOS with a focus on achieving the lowest possible phase noise using only a single core and maintaining the recommended Vdd of the technology. The oscillator consists of a cross-coupled design utilizing a transformer-coupled resonant tank, which takes advantage of tank parasitics to create harmonic resonances. An analysis is offered, which justifies the use of the transformer tank, noting its importance in mitigating the practical limits imposed during layout on equivalent $LC$ tanks. An excellent phase noise of −122 dBc/Hz is measured at 1 MHz offset from the carrier resulting in a figure of merit (FoM) and tuning FoM (FoMT) of −183 and −190 dBc/Hz, respectively. The VCO is incorporated into a type-II charge-pump-based phase-locked loop (PLL) with intent to be used as the local oscillator (LO) generation in a potential fifth-generation (5G) communication system.

A 14-bit 4-MS/s VCO-Based SAR ADC With Deep Metastability Facilitated Mismatch Calibration

Abstract: This article presents a 14-bit 4-MS/s voltage-controlled oscillator (VCO)-based successive approximation register (SAR) analog-to-digital converter (ADC), where the metastability of the VCO-based comparator is exploited for the background calibration of mismatch errors. A closed-form behavioral analysis of VCO-based comparators has been studied in the presence of noise, showing that the metastability is of unique characteristics as compared to voltage-domain comparators, and the metastability can be evaluated quantitatively by observing the number of oscillation cycles. Deep metastability (DM) indicates a condition where the signal and noise are sufficiently small as compared to mismatch errors, based on which an analog background calibration technique is proposed. A decision stabilizer is employed to deal with the limit-cycle oscillations (LCOs). Fabricated in a 40-nm CMOS technology, the ADC prototype exhibits peak signal-to-noise-and-distortion ratio (SNDR) of 78.7 dB and >93-dB spurious-free dynamic range (SFDR) across nine samples. At 2 and 4 MS/s, the ADC, including calibration logic, consumes only 94 and $157~\mu \text{W}$ from a 1.1-V supply, achieving a peak Schreier figure of merit (FoM) of and 177.7 dB, respectively.

A Wearable Real-Time CMOS Dosimeter With Integrated Zero-Bias Floating Gate Sensor and an 861-nW 18-Bit Energy-Resolution Scalable Time-Based Radiation to Digital Converter

Abstract: Radiation, being invisible and odorless, has become a major concern in modern-day healthcare, mining, security, and nuclear applications that require professionals to work in environments involving radioactive materials, often with only elementary training. Furthermore, the scenario is worsened by the absence of a real-time, accumulative radiation dosimeter of small/wearable form factor that can provide direct digital output for long-term continuous monitoring. In this article, we present the first monolithically integrated CMOS wearable radiation dosimeter, consisting a floating-gate (FG) resistive sensor with a sensitivity of 14 $\Omega $ /rad, and a time-domain resistance-to-digital-converter (RDC) that functions as an 18-bit voltage-controlled oscillator (VCO)-based ADC, consuming 861 nJ for 10-ms active read time (which translates to 861-nW at 1 S/s), with 3.29-pJ/conversion step energy efficiency. The proposed time-based RDC exhibits programmable energy-resolution scalability by controlling the measurement time (unlike traditional voltage/current-mode ADCs) and achieves 6-bit better resolution than the state-of-the-art VCO-based ADCs at low frequency (conversion time ≈10 ms). The implemented integrated dosimeter achieves 8-bit better resolution, 7.5 $\times $ lower power, and 40 $\times $ better sensitivity (up to 10-mrad dose) than the current CMOS FG dosimeters.

A 2.4 GHz ISM Band OOK Transceiver With High Energy Efficiency for Biomedical Implantable Applications

Abstract: This article presents a high energy efficiency, high-integrated, and low-power on–off keying transceiver for a 2.4 GHz industrial scientific medical band. The proposed receiver includes an input matching network, a low-noise amplifier, a novel single-to-differential envelope detector, a level shifter, cascaded baseband amplifiers, and a hysteresis comparator. The proposed transmitter includes a bias-stimulating circuit, a current-reused self-mixing voltage controlled oscillator, and a quadruple-transconductance power amplifier. Numerous proposed techniques implemented in the mentioned circuits improve the energy per bit and power efficiency. Therefore, the proposed receiver for short-distanced propagation can achieve a sensitivity of −46 dBm with a carrier frequency of 2.45 GHz and a high data rate of 2 Mbps. The proposed transmitter achieves an output power of −17 dBm with a high data rate of 20 Mbps. This work is fabricated in a TSMC 0.18 μm CMOS process and consumes 160 μW and 0.6 mW in the receiver and transmitter, respectively, from a 1.2 V supply voltage. The energy per bit of 80 pJ/bit in the receiver part and the figure of merit of 9 in the transmitter part are better than those of existing state-of-the-art transceivers.

A Highly Linear OTA-Less 1-1 MASH VCO-Based $\Delta\Sigma$ ADC With an Efficient Phase Quantization Noise Extraction Technique

Abstract: In this article, an efficient technique is introduced to extract the quantization noise of a multi-phase voltage-controlled oscillator (VCO)-based quantizer (VCOQ) in the time domain as a pulsewidth modulated (PWM) signal. Using this technique, a new highly linear VCO-based 1-1 multi-stage noise shaping (MASH) delta–sigma analog-to-digital converter (ADC) structure is presented. This architecture does not require any operational transconductance amplifier (OTA)-based analog integrators or power-hungry linearization methods. The first stage is a closed-loop multi-phase VCO-based voltage-to-phase (V-to-P) converter, and the second stage is an open-loop multi-phase VCO-based voltage-to-frequency (V-to-F) converter. Using the proposed technique, the phase quantization error of the first stage is extracted as a pulse signal and then fed to the second stage. The input of the first VCO is a very small amplitude signal, and the input of the second VCO is a two-level PWM signal. Therefore, the VCO non-linearity does not limit the overall ADC performance, mitigating the need for power-hungry linearization methods. The prototype achieves second-order noise shaping with a DR/SFDR/SNR/SNDR of 82.7/88.7/80.3/79.7 dB for an input signal BW of 2 MHz. The fabricated design consumes 1.248 mW from a 0.9-V supply.

A 210–284-GHz I–Q Receiver With On-Chip VCO and Divider Chain

Abstract: A 240-GHz direct conversion I–Q receiver with 74-GHz RF bandwidth is reported. It features a mixer-first architecture with fundamental local oscillator (LO)-frequency Gilbert-cell downconversion mixers, variable-gain baseband amplifiers, and a 240-GHz LO source, making it the first fully integrated 240-GHz I–Q receiver. With a phase noise of −82 dBc/Hz at 1-MHz offset, the LO source has a 27-GHz tuning range and consists of a 120-GHz voltage-controlled oscillator (VCO), a frequency doubler, and a static divide-by-128 chain. The measured peak downconversion gain is 23 dB and is adjustable over 38 dB. Along with the IF bandwidth of 59 GHz, the wide RF bandwidth makes it suitable for both high data-rate communication and emerging quantum computing applications. The chip occupies an area of 1.837 mm2 and consumes 859 mW.

A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC With Dual Rising-Edge Fractional-Phase Detector

Abstract: A 77-GHz frequency-modulated continuous-wave (FMCW) generator is presented for millimeter-wave (mm-wave) radar applications. The FMCW chirp is provided by a mixed-mode phase-locked loop (PLL). A dual rising-edge fractional-phase detector based on time-to-digital converter (TDC) is proposed to overcome the problem caused by the rising and falling time mismatch. A 2.3 ns detection range, 10 ps resolution Vernier TDC is employed in the detector to cover the two consecutive rising edges with less power consumption. A self-calibrated delay chain is employed in the Vernier TDC to overcome process, voltage and temperature (PVT) variations. Furthermore, sampling-edge selection technique is utilized to avoid the glitch during phase detection. A divider-less frequency error estimator is presented to save area and power. By employing a coarse-fine segmented digital-to-analog converter (DAC), the generator supports triangular and sawtooth-like FMCW chirp with reconfigurable period and bandwidth. An LC voltage- controlled oscillator (VCO) with split varactor is proposed to improve the linear tuning range. Implemented in 65 nm CMOS, the FMCW generator consumes 99 mW power and 0.7 mm $\times $ 0.8 mm chip area. The measurement results show that the phase noise from 78.7 GHz carrier is −87.4-dBc/Hz at 1 MHz offset. The measured root-mean-square (RMS) frequency error of a sawtooth-like FMCW chirp with 4 GHz bandwidth and 0.1 ms period is 205 kHz.

Enhanced Digital Synthesized Phase Locked Loop with High Frequency Compensation and Clock Generation

Abstract: The proposed work concentrates on the integration of an 8-GHz voltage-controlled oscillator (VCO) and a frequency tripler for 24-GHz local oscillator generation. By stacking the VCO and the tripler with a current-reused topology, the power consumption of this integration can be saved. The proposed circuit with a total chip area of 0.7 mm ×0.8 mm is implemented in a 0.18 μm CMOS process. As the tuning voltage increases from 0 to 2 V, the measured frequency tuning range (FTR) of the VCO is from 7.06 to 8.33 GHz. The final resulting output frequency from the tripler ranges from 21.18 to 24.98 GHz (16.5% FTR). The core circuit totally consumes 5 mA from a 1.8-V supply voltage. The measured phase noises at the VCO and frequency tripler outputs are − 113.76 and − 105.1 dBc/Hz at 1-MHz offset frequency, respectively, when Vtune is 0 V. The best evaluated figure of merit with tuning is − 187.2 dBc/Hz (decibels relative to carrier). Closed form equations allow for a performance driven design for both PLL and estimator. By using a variable sample frequency controlled by the PLL, the Kalman filter is always operated around its center frequency, which is the rated grid frequency. The new topology is compared to other published single-phase PLL designs and its operation is verified by both simulations and experiments. This integration of a VCO and a frequency tripler exhibits a high potential for the use in low-power 24-GHz phase-locked loops. The PLL designed using dual mode logic technique exhibits excellent performance even under severely distorted utility grid voltage conditions. This robustness makes it very suitable for use in systems connected to grids having an important share of non-linear loads.

An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter

Abstract: This article presents an incremental two-step capacitance-to-digital converter (CDC) with a time-domain $\Delta \Sigma $ modulator (TD $\Delta \Sigma \text{M}$ ). Unlike the classic two-step CDCs, this work replaces the operational transconductance amplifier (OTA)-based active- RC integrator by a voltage-controlled oscillator (VCO)-based integrator, which is mostly digital and low-power. Featuring the infinite dc gain and intrinsic quantization in phase domain, this TD $\Delta \Sigma \text{M}$ enables a CDC design achieving 76-dB SNDR while requiring only a first-order loop, and a low oversampling ratio (OSR) of 15. Fabricated in 40-nm CMOS technology, the prototype CDC achieves a resolution of 0.29 fF while dissipating only 0.083 nJ/conversion, which improves the energy efficiency by over two times comparing to the similar performance designs.

28 GHz balanced pHEMT VCO with low phase noise and high output power performance for 5G mm-Wave systems

Abstract: This paper presents the study and design of a balanced voltage controlled oscillator VCO for 5G wireless communication systems. This circuit is designed in monolithic microwave integrated circuit (MMIC) technology using PH15 process from UMS foundry. The VCO ensures an adequate tuning range by a single-ended pHEMT varactors configuration. The simulation results show that this circuit delivers a sinusoidal signal of output power around 9 dBm with a second harmonic rejection between 25.87 and 33.83 dB, the oscillation frequency varies between 26.46 and 28.90 GHz, the phase noise is -113.155 and -133.167 dBc/Hz respectively at 1 MHz and 10 MHz offset and the Figure of Merit is -181.06 dBc/Hz. The power consumed by the VCO is 122 mW. The oscillator layout with bias and RF output pads occupies an area of 0.515 mm2.

17.9 A 9mW 54.9-to-63.5GHz Current-Reuse LO Generator with a 186.7dBc/Hz FoM by Unifying a 20GHz 3 rd -Harmonic-Rich Current-Output VCO, a Harmonic-Current Filter and a 60GHz TIA

Abstract: Low-power mm-wave sensors using an FMCW radar technology are opening up unprecedented opportunities in high-resolution object detection (e.q., gesture and breathing). Building a low-power mm-wave LO generator (LOG) fulfilling the stringent phase-noise (PN) requirement of the FMCW transceiver is still challenging [1]. A number of indirect mm-wave LOGs have been explored. As depicted in Fig. 17.9.1, a 20GHz VCO followed by a frequency tripler (x3) effectively lowers the PLL operating frequency by 3 times, benefiting not only the power budget but also the frequency-tuning range. Injection locking [2], harmonic-mixing [3], and voltage-mode implicit frequency tripling [4] are the mainstream x3 techniques, where the first technique faces the trade-off between locking range and output power, whereas the second and third techniques call for a power-hungry mm-wave mixer or amplifier to recover a large output swing. Finally, all of them suffer from severe subharmonic spurs.