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Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.


Papers
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Journal ArticleDOI
05 Feb 2001
TL;DR: A fully integrated CMOS transceiver tuned to 2.1 GHz consumes 46 mA in receive-mode and 47mA in transmit-mode from a 2.7 V supply and delivers a GFSK modulated spectrum at an output power of 5 dBm.
Abstract: A fully integrated CMOS transceiver tuned to 2.4 GHz consumes 46 mA in receive mode and 47 mA in transmit mode from a 2.7-V supply. It includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), power amplifier, and demodulator. The receiver uses a low-IF architecture for higher level of integration and lower power consumption. It achieves a sensitivity of -82 dBm at 0.1% BER, and a third-order input intercept point (IIP3) of -7 dBm. The direct-conversion transmitter delivers a GFSK modulated spectrum at a nominal output power of 4 dBm. The on-chip voltage controlled oscillator has a close-in phase-noise of -120 dBc/Hz at 3-MHz offset.

220 citations

Journal ArticleDOI
TL;DR: In this article, a simple analysis relates the small-signal specification of a varactor's capacitance to an oscillator's tuning curve and explains how the varactor converts AM noise on the oscillation into FM, which is phase noise.
Abstract: A simple analysis relates the small-signal specification of a varactor's capacitance to an oscillator's tuning curve. The notion of an effective capacitance across the amplitude of oscillation is introduced. The analysis also explains how the varactor converts AM noise on the oscillation into FM, which is phase noise. The analysis is experimentally validated.

219 citations

Journal ArticleDOI
19 Feb 1992
TL;DR: In this article, the authors describe a completely monolithic delay-locked loop (DLL) which may be used either by itself as a deskewing element or in conjunction with an external voltage-controlled crystal oscillator (VCXO) for a delay- and phase-locked LLL that enables jitter-peaking-free clock recovery by removing the zero from the forward path.
Abstract: The authors describe a completely monolithic delay-locked loop (DLL) which may be used either by itself as a deskewing element or in conjunction with an external voltage-controlled crystal oscillator (VCXO) for a delay- and phase-locked loop (D/PLL) that enables jitter-peaking-free clock recovery by removing the zero from the forward path. The voltage-controlled phase shifter (VCPS) shifts incoming data under loop control to align the data with the clock. The loop amplifier is an integrator so that the DLL is first order. The bandwidth of the loop determines the frequencies over which input jitter may be tracked out. The phase detector is a pattern-and duty-cycle insensitive implementation. The higher-order poles provide additional filtering of phase-detector output ripple to further improve jitter accommodation. >

217 citations

Journal ArticleDOI
TL;DR: In this paper, phase noise mechanisms in integrated LC voltage-controlled oscillators (VCOs) using MOS transistors are investigated, and the degradation in phase noise due to low-frequency bias noise is shown to be a function of AM-PM conversion in the MOS switching transistors.
Abstract: Phase noise mechanisms in integrated LC voltage-controlled oscillators (VCOs) using MOS transistors are investigated. The degradation in phase noise due to low-frequency bias noise is shown to be a function of AM-PM conversion in the MOS switching transistors. By exploiting this dependence, bias noise contributions to phase noise are minimized through MOS device sizing rather than through filtering. NMOS and PMOS VCO designs are compared in terms of thermal noise. Short-channel MOS considerations explain why 0.18-/spl mu/m PMOS devices can attain better phase noise than 0.18-/spl mu/m NMOS devices in the 1/f/sup 2/ region. Phase noise in the 1/f/sup 3/ region is primarily dependent upon the upconversion of flicker noise from the MOS switching transistors rather than from the bias circuit, and can be improved by decreasing MOS switching device size. Measured results on an experimental set of VCOs confirm the dependencies predicted by analysis. A 5.3-GHz all-PMOS VCO topology demonstrates measured phase noise of -124 dBc/Hz at 1-MHz offset and -100dBc/Hz at 100-kHz offset while dissipating 13.5 mW from a 1.8-V supply using a 0.18-/spl mu/m SiGe BiCMOS process.

216 citations

Journal ArticleDOI
TL;DR: This paper describes the design of CMOS millimeter-wave voltage controlled oscillators and shows the lumped element approach can be used even for VCOs operating near 100-GHz and it results a smaller circuit area.
Abstract: This paper describes the design of CMOS millimeter-wave voltage controlled oscillators. Varactor, transistor, and inductor designs are optimized to reduce the parasitic capacitances. An investigation of tradeoff between quality factor and tuning range for MOS varactors at 24 GHz has shown that the polysilicon gate lengths between 0.18 and 0.24 /spl mu/m result both good quality factor (>12) and C/sub max//C/sub min/ ratio (/spl sim/3) in the 0.13-/spl mu/m CMOS process used for the study. The components were utilized to realize a VCO operating around 60 GHz with a tuning range of 5.8 GHz. A 99-GHz VCO with a tuning range of 2.5 GHz, phase noise of -102.7 dBc/Hz at 10-MHz offset and power consumption of 7-15mW from a 1.5-V supply and a 105-GHz VCO are also demonstrated. This is the CMOS circuit with the highest fundamental operating frequency. The lumped element approach can be used even for VCOs operating near 100-GHz and it results a smaller circuit area.

216 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023168
2022344
2021269
2020388
2019469
2018530