Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.

A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer

Abstract: Voltage-controlled oscillator (VCO) based analog-to-digital conversion presents an attractive means of implementing high-bandwidth oversampling ADCs [1,2]. They exhibit inherent noise-shaping properties and can operate at low supply voltages and high sampling rates [1–3]. However, usage of VCO-based ADCs has been limited due to their nonlinear voltage-to-frequency (V-to-F) transfer characteristic, which severely degrades their distortion performance. Digital calibration is used to combat nonlinearity in an open-loop VCO-based ADC, but 1st-order noise-shaping mandates high OSRs, thus increasing power dissipation in digital circuits, even in a nanometer-scale CMOS process [1]. In [2], nonlinearity is suppressed by embedding the VCO in a ΔΣ loop. While this technique works in principle, the need for large loop gain at high frequencies makes it very difficult to achieve high SNDR. For instance, the suppression level near the band edge is approximately 20dB for a VCO-based 2nd-order modulator operating with an over-sampling ratio (OSR) of 30. Our ADC overcomes the impact of VCO non-linearity by minimizing the input signal processed by the VCO. The prototype achieves 78.3dB SNDR in a 10MHz signal bandwidth at 600MHz sampling rate, while consuming 16mW power.

A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS

Abstract: A 40 MHz-BW 10 bit two-step VCO-based Delta-Sigma ADC is presented. With the open-loop structure and highly digital building blocks, a robust performance, high bandwidth and high power efficiency are achieved. The nonlinearities of the coarse and the fine VCO-based quantizers are mitigated by distortion cancellation and voltage swing reduction schemes respectively. Because of the intrinsic DEM of the VCO-based quantizer output, the matching requirement of the DAC cells is greatly relaxed. The experimental results in 40 nm CMOS show that, with 1.6 GHz sampling frequency, the proposed ADC reaches 59.5 dB SNDR and 67.7 dB SFDR for 40 MHz bandwidth. The power consumption is only 2.57 mW under 0.9 V power supply, corresponding the best FoM (42 fJ/step) among high bandwidth ( 20 MHz) DS ADCs.

An injection-locked ring PLL with self-aligned injection window

Abstract: In modern analog front-ends, there is an increasing demand on high-performance analog-to-digital converters (ADCs), which require high sampling frequency and low-jitter sampling clock. This makes low-jitter phase-locked loops (PLLs) with jitter on the order of few picoseconds desirable. Unfortunately, due to stringent limit on die area, sometimes a PLL with a ring oscillator is the only choice. To get better phase noise, a wider loop bandwidth is needed to suppress the noise of the voltage-controlled oscillator (VCO). However, due to the discrete-time nature of the operations, the loop bandwidth is limited to one-tenth of the crystal oscillator (XTAL) frequency. One way to solve this problem is to use the injection-locking technique. This method exploits the clean reference clock but has several production problems. One is the frequency offset between injection signal and VCO, and this can be solved by using the injection-locked PLL architecture [1, 2]. However, in [1, 2] extra loops are still needed to adjust the injection window due to on-chip variations. In this work, an injection-locked ring PLL (ILRPLL) architecture is proposed to solve this problem. Using the concept of sub-sampling PLLs [3], the injection window is aligned automatically without feedback adjustment. A 432MHz ILRPLL is realized in ATV/DTV system to justify this technique.

RF signal generator

Abstract: An RF test signal generator including a driving oscillator, a pulse generr for generating narrow spikes at the oscillator frequency (such as a step recovery diode), a modulator and an attenuator. Since the very narrow pulse exhibits nearly constant amplitude in the frequency domain, a constant amplitude comb spectrum with frequency spacing at the oscillator frequency is generated so as to facilitate automated testing techniques.

GHz transceiver phase lock loop having autofrequency lock correction

Abstract: A transceiver circuit used in connection with a fiber channel serial interface is designed and constructed with transmitter and receiver phase lock loop sections, each acquiring velocity lock with respect to a 106.25 MHz reference clock signal. The transmitter phase lock loop section is maintained in velocity lock during serialization of a 10-bit encoded transmission character. The receiver phase lock loop section is operative in a phase-only mode during de-serialization and byte synchronization of a 1.0625 GHz serial data stream. VCO control voltages of both the transmitter and receiver phase lock loop sections are monitored and evaluated by a comparison circuit such that if the receiver phase lock loop section looses lock, its VCO control voltage will exceed a pre-determined lock range value, triggering an output of the comparison circuit. The output trigger of the comparison circuit automatically commands the receiver phase lock loop section to reacquire velocity lock and maintains the receiver phase lock loop section in velocity lock mode until such time as the receiver VCO control voltage returns to about its nominal value. Frequency lock correction is applied to the receiver phase lock loop section automatically and is a function solely of the receiver phase lock loop frequency deviation from its nominal value.