Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.

Compensation for oscillator tuning gain variations in frequency synthesizers

Abstract: A system is provided for compensating for tuning gain variations in a phase lock loop. Compensation is performed by a calibration system that estimates the tuning gain of the oscillator and then adjusts the charge pump current value by a ratio of the nominal tuning gain to the measured tun gain. The tuning gain measurement is performed by measuring the change in the voltage controlled oscillator's tuning control voltage when the phase lock loop is locked to two different frequencies, which are separated by a fixed, predetermined amount. The two frequencies may be above or below the final output frequency of the VCO, or the second frequency may be the final frequency in order to reduce calibration time and settling time.

A 0.9-2.2 GHz monolithic quadrature mixer oscillator for direct-conversion satellite receivers

Abstract: External tank circuits including varicaps are often employed in satellite receiver ICs. These circuits require external components and an expensive 30 V tuning voltage supply. This fully-integrated quadrature current-controlled oscillator (QCCO), quadrature mixer, and V/I converter with band switch circuit uses a standard BiCMOS process, (f/sub /spl sim//5GHz) the tuning range of 80% covers the satellite band with a VCO gain of 150MHz/V/spl plusmn/35%. The band switch circuit divides the frequency range of 0.9-2.2 GHz into four bands, each with a tuning voltage range from 0 V up to 3.5 V.

High frequency receiving apparatus

Abstract: A high frequency television signal receiving apparatus providing excellent linear detection of output characteristics by improving the phase characteristic of the picture synchronous detector. A variable capacitive element is equivalently connected in parallel to a reference solid-state oscillation element. The reference solid-state oscillation element controls the frequency of a local oscillation device including a PLL circuit for feeding a local oscillation signal to a mixer for converting a high frequency signal into an intermediate frequency signal. A first low pass filter is connected between a phase comparator for detecting a phase difference of the intermediate frequency signal and the output of a detection oscillator for generating a detection oscillation signal with a specific phase difference. A second low pass filter having a larger time constant than the first low pass filter is connected to the variable capacitive element. The capacitance of the variable capacitive element is varied by the output voltage of the phase comparator. The signal frequency of the local oscillation device is shifted, and is controlled to converge the frequency of the intermediate frequency signal within the frequency range of the detection oscillation signal.

A 2.6 GHz/5.2 GHz CMOS voltage-controlled oscillator

Abstract: New wireless local area network (WLAN) standards have recently emerged in the 5 GHz band. For example, high performance radio LAN (HIPERLAN) is a European standard operating at 5.2 GHz with Gaussian minimum shift keying (GMSK) modulation and a 23 MHz channel bandwidth. The voltage-controlled oscillator reported here is to be used in a HIPERLAN transceiver. Here, the receiver employs two downconversion steps, each with a 2.6 GHz local oscillator (LO) frequency, translating the RF spectrum to dc. The second downconversion thus requires the quadrature phases of the LO. The transmitter performs modulation by first placing the VCO in a synthesizer loop and subsequently opening the loop and applying the Gaussian-shaped baseband data to the VCO to perform GMSK modulation.

A "flying-adder" architecture of frequency and phase synthesis with scalability

Abstract: Most of today's digital designs, from small-scale digital block designs to system-on-chip (SoC) designs, are based on "synchronous" design principle. Clock is the most important issue in these designs. Frequency and phase synthesis is closely related to the clock generation. A frequency and phase synthesis technique based on phase-locked loop is proposed in that delivers high performance, easy integration, and high stability. However, there are problems associated with this architecture, such as: 1) its highest deliverable frequency is limited by the speed of the accumulator and 2) the phase synthesis circuitry will not work well in certain ranges (dead zone) and in certain conditions (dual stability). This paper presents an improved architecture that addresses these problems. The new frequency synthesis circuitry has scalability for higher output frequency. It also has an internal node whose frequency is twice that of output signal. When duty cycle is not a concern, this signal can be used directly as clock source. The new phase synthesis circuitry is free of "dead zone" and "dual stability." The improved architecture has better performance, is simpler to implement, and is easier to understand.