Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.

Ultrasonic power supply

Abstract: An ultrasonic power supply for driving a piezoelectric transducer at its parallel resonant frequency includes a clamped-mode resonant converter for converting direct current to alternating current and a demodulator, a loop filter and a voltage controlled oscillator in a phase locked loop configuration. The power supply also includes a control circuit for adjustably setting and controlling the amplitude of vibration of the transducer, and providing during start-up a ramp start. The power supply, further, includes a control circuit for limiting the maximum permissible current flow to the transducer and the reverse current flow from the transducer resulting from stored mechanical energy. Both control circuits provide feedback signals which control the pulse width modulated operation of the clamped-mode resonant converter and thereby control the voltage amplitude of the alternating current output from the converter. The phase locked loop circuit causes the frequency of the alternating current output from the converter to track the parallel resonant frequency of the transducer.

A 60-GHz CMOS VCO Using Capacitance-Splitting and Gate–Drain Impedance-Balancing Techniques

Abstract: The design and measurement of a 60-GHz 90-nm CMOS voltage-controlled oscillator is presented. To reduce the power consumption and to improve the phase-noise performance, a capacitance-splitting and a gate-drain impedance-balancing techniques, which are realized with an inductive divider, are proposed. With these techniques, the size of the cross-coupled pair is reduced. Analysis of the proposed techniques shows that the transistor g m generation efficiency is improved and the oscillator noise factor is reduced. Moreover, the tank loaded quality factor is increased by balancing impedance levels across the transistor terminals. The 60-GHz oscillator was fabricated in a 90-nm CMOS technology. Under 0.6-V supply, the oscillator achieved a tuning range from 61.1 to 66.7 GHz, consuming only 3.16 mW. At 64 GHz, the phase noise is -95 dBc/Hz at 1-MHz offset.

Apparatus for reducing jitter of a spectrum spread clock signal and method therefor

Abstract: An accumulator stores a signal representation of an accumulated angle that is incremented by an input angle in response to a reference clock pulse. The most significant bit (MSB) of the accumulated angle signals drives the input of a phase locked loop of the type that includes a loop filter, a frequency divider and a voltage controlled oscillator (VCO). A charge is injected into the loop filter during an overshoot interval during which the output of the frequency divider differs from the MSB. A compensating charge is injected into the loop filter to compensate for the charge injected during the overshoot interval. Jitter free spectrum spread clock pulses are provided by the VCO in response to the MSB.

Voltage controlled oscillator (VCO) with symmetrical output and logic gate for use in same

Abstract: A voltage controlled oscillator (VCO) (23) includes a periodic signal generator (30) such as a comparator (42)followed by a latch (43), and a logic gate such as a NAND gate (31) connected to the output of the latch (43) to adjust for asymmetries in the output signals from the latch (43). In one embodiment, the NAND gate (31) includes two pullup transistors (80, 81) receiving first and second output signals from the latch and connected between a first power supply voltage terminal and an output node (86). Two switching branches (82, 83 and 84, 85) each including two transistors are connected between the output node (86) and a second power supply voltage terminal. The order of the input signals received by the two transistors is reversed between the two switching branches (82, 83 and 84, 85) to compensate for any duty cycle asymmetries. A frequency divider (32) divides the output of the NAND gate (31) to complete the duty cycle adjustment.

Digital temperature-compensated oscillator

Abstract: A digital temperature-compensated oscillator comprises a crystal oscillator, a first memory previously storing digital temperature compensation data obtained by previously measuring the relation between the ambient temperatures and the frequency deviations of the crystal oscillator, a second memory for storing frequency offset amounts of the oscillation frequency of the crystal oscillator, a temperature sensor for outputting analog detection data relating to the ambient temperature, an A/D converter for converting the analog detection data to digital detection data, a readout circuit for reading out temperature compensation data corresponding to the digital detection data and stored in the first memory according to the digital detection data and reading out the frequency offset amount stored in the second memory according to the digital detection data, an operation circuit for effecting the following calculation by use of the readout temperature compensation data and readout frequency offset amount to derive digital control voltage, V.sub.c =V.sub.co +(K.sub.00 +V.sub.co K.sub.10 +K.sub.01 T)×(ΔF+ΔF 2 ×K 10 /2) where K 00 , K 01 and K 10 are constants, V co is an initial value of the control voltage, T is an ambient temperature and ΔF is a frequency offset amount, a D/A converter for converting the digital control voltage into an analog control voltage, and a voltage-capacitance converter for receiving the analog control voltage and generating a control signal to be supplied to the crystal oscillator according to the received analog control voltage, wherein the frequency of the crystal oscillator is controlled according to the control signal.