Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.

A 86 MHz–12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS

Abstract: A 86 MHz-12 GHz digital-intensive reconfigurable PLL frequency synthesizer is presented with 100 kHz to 2 MHz bandwidth. It leverages a 6 fJ/step 5.5 ps, 14b coarse-fine TDC and a 6-12 GHz dual-VCO set. Several simple calibration schemes are proposed that enable the proper performance of the highly efficient TDC in the PLL. The 0.28 mm2 synthesizer, which is appropriate for use in a Software-Defined Radio, features noise cancellation and digital phase modulation and consumes less than 30 mW.

A 131 GHz push-push VCO in 90-nm CMOS technology

Abstract: A 131 GHz cross-coupled push-push voltage controlled oscillator (VCO) is realized in 90-nm CMOS technology. It can be tuned from 129.8 to 132 GHz, with an estimated phase noise of -108.4 dBc/Hz at 10 MHz offset. The oscillator provides a push-push output power of -15.2 dBm and a fundamental output power of +0.33 dBm, under core current of 20 mA from a 1-V supply voltage. Maximum push-push and fundamental output powers are -11.4 dBm and +2.1 dBm, respectively. To the authors' knowledge, this is the highest frequency CMOS VCO ever reported.

Phase locked loop using a schmitt trigger block

Abstract: A phase locked loop (PLL) circuit is described which uses a Schmitt trigger block (28) to achieve a very small steady state phase error at an input of a phase comparator block (21) over the entire PLL lock voltage range. The amount of hysteresis which each Schmitt trigger circuit (281, 282) in the Schmitt trigger block (28) has depends on the damping factor ζ of the PLL circuit as well as the temperature and voltage coefficients of a VCO's input voltage. The midpoint of the positive and the negative thresholds of the hysteresis curve of each Schmitt trigger circuit (281, 282) is set by the current voltage characteristics of charge pump circuits in a charge pump block (22). Responsive to the PLL's lock voltage (VCNT), the Schmitt trigger block (28) commands a control logic circuit (29) to turn ON or turn OFF as the case may be PMOS pump UP transistors to that of NMOS pump DOWN transistors. It is this ratio which determines the PLL's steady state phase error. In one embodiment, a frequency divider (25) is used between the VCO (24) and the phase comparator block (21). In another embodiment, this divider (25) is removed and the output of the VCO is fed directly back to the phase comparator block.

A 140-GHz double-sideband transceiver with amplitude and frequency modulation operating over a few meters

Abstract: This paper describes the first demonstration of Doppler detection and data transmission at 140 GHz and 4 Gb/s through the air using a single-chip silicon transceiver at 140 GHz. The transceiver, which consists of a 140-GHz push-push VCO with a static divide-by-64 chain, a 140-GHz amplitude modulator, a 140-GHz LO amplifier, a fundamental frequency mixer, a 140-GHz LNA, and a variable gain IF amplifier, has a downconversion gain of 30 dB and a noise figure of 12.3 dB. It is fabricated in a 130-nm SiGe BiCMOS technology, occupies an area of 1.44 mm2, and consumes 1.5 W.

On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures

Abstract: Performance variability in digital integrated circuits can largely affect parametric yield and product reliability in ultra deep submicrometer technologies. As a result, variation resilience is becoming an essential design requirement for future technology nodes, especially for timing critical applications. This paper proposes an on-chip variability sensor using phase-locked loop (PLL) to detect process, supply voltage (V DD), and temperature variations (process, voltage, and temperature variation) or even temporal reliability degradation stemming from negative bias temperature instability. Our analysis shows that control voltage (V cnt) of voltage-controlled oscillator in PLL can be used as a dynamic performance signature of an operating IC. Along with the proposed PLL-based sensor circuit, we also propose a variation-resilient system technique using adaptive body biasing (ABB). The PLL V cnt signal is efficiently transformed to an optimal body bias signal for various circuit blocks to avoid possible timing failures. Correspondingly, circuits can be designed with significantly relaxed timing constraint compared to conventional approaches, where a large amount of design resources can be wasted to take care of the worst-case situations. We demonstrated our approach on a test chip fabricated in IBM 130-nm CMOS technology. Measurement results show that the PLL-based sensor is cable of tracking various sources of circuit variations. Optimization analysis shows that 42% and 43% reduction in area and power can be obtained using our approach compared to the worst-case sizing. The proposed study refers to our previous study introduced in with major improvements in measurement results and analysis.