Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.

Clock recovery phase lock loop having digitally range limited operating window

Abstract: A PLL architecture is disclosed which incorporates a coarse adjustment feedback loop and a fine adjustment feedback loop together providing a combined error signal to a single VCO. The coarse adjustment feedback loop includes two digital counters set to divide the VCO output frequency by two different numbers. The outputs of the counters are coupled to the inputs of respective phase-frequency detectors, and the pump-up output of one of the detectors and the pump-down output of the other detector are used as the coarse adjustment pump-up and pump-down signals, respectively, in the coarse adjustment feedback loop. The coarse adjustment feedback loop thereby establishes a frequency range limitation for the fine adjustment feedback loop.

Voltage controlled oscillator with frequency sensitivity control

Abstract: A voltage controlled oscillator is tuned with a network comprising two varactor diodes and two transmission lines. By selecting appropriate values of varactor capacitance and transmission line length and width the overall reactance of the network is such that, when a varactor tuning voltage is varied, the output frequency of the voltage controlled oscillator will vary in an fashion with respect to the tuning voltage. Such a voltage controlled oscillator is gain compensated and exhibits a controlled modulation sensitivity over a range of frequencies. If the required frequency range of the oscillator is known beforehand, an alternate embodiment of the invention may be employed in which one of the varactor diodes is replaced with a fixed capacitor having a suitable value for the desired frequency range.

Pll frequency synthesizer capable of changing an output frequency at a high speed

Abstract: In a frequency synthesizer, a first pulse removing circuit (31) is connected between a reference signal generator (21) and a phase-frequency comparator (24). A second pulse removing circuit (32) is connected between a variable frequency divider (23) and the phase-frequency comparator. Responsive to first removing data indicative of a first pulse number, the first pulse removing circuit removes pulses from the reference signal that are equal in number to the first pulse number for a first predetermined cycle to produce a first pulse removed signal. Responsive to second removing data indicative of a second pulse number, the second pulse removing circuit removes pulses from the divided signal that are equal in number to the second pulse number for a second predetermined cycle to produce a second pulse removed signal. Responsive to a current command, a current controlling circuit may control current supplied from/to a charge pump circuit (25). A control circuit may be connected between the phase-frequency comparator and the charge pump circuit. A switch may be inserted between the loop filter and the voltage controlled oscillator. When the switch switches off a PLL, a D/A converter supplies a control voltage to the voltage controlled oscillator and a filter capacitor of the loop filter. The charge pump circuit may comprise a control circuit, a constant current circuit, an integrating circuit, and a sample and hold circuit.

High Frequency Buck Converter Design Using Time-Based Control Techniques

Abstract: Time-based control techniques for the design of high switching frequency buck converters are presented. Using time as the processing variable, the proposed controller operates with CMOS-level digital-like signals but without adding any quantization error. A ring oscillator is used as an integrator in place of conventional opamp-RC or G $_{\rm m}$ -C integrators while a delay line is used to perform voltage to time conversion and to sum time signals. A simple flip-flop generates pulse-width modulated signal from the time-based output of the controller. Hence time-based control eliminates the need for wide bandwidth error amplifier, pulse-width modulator (PWM) in analog controllers or high resolution analog-to-digital converter (ADC) and digital PWM in digital controllers. As a result, it can be implemented in small area and with minimal power. Fabricated in a 180 nm CMOS process, the prototype buck converter occupies an active area of 0.24 mm $^{2}$ , of which the controller occupies only 0.0375 mm $^{2}$ . It operates over a wide range of switching frequencies (10–25 MHz) and regulates output to any desired voltage in the range of 0.6 V to 1.5 V with 1.8 V input voltage. With a 500 mA step in the load current, the settling time is less than 3.5 $\mu$ s and the measured reference tracking bandwidth is about 1 MHz. Better than 94% peak efficiency is achieved while consuming a quiescent current of only 2 $\mu$ A/MHz.

A fully integrated zero-IF transceiver for GSM-GPRS quad band application

Abstract: A GPRS GSM850/GSM/DCS/PCS fully integrated transceiver occupies 14mm/sup 2/ in 0.35/spl mu/m SiGe technology. A direct conversion receiver, transmitter, synthesizer, VCO, voltage regulators and loop filters are fully integrated. The chip meets the GPRS specifications including settling time of 105/spl mu/s in RX mode, NF of 3dB for GSM, TX phase error of 2/spl deg/ RMS, and PLL phase noise of -84dBc/Hz at a 1kHz offset at 3.6GHz.