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Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.


Papers
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Journal ArticleDOI
TL;DR: This brief covers the design and fabrication of a ring oscillator-based truly random number generator (TRNG), which was fabricated in 0.13-μm CMOS technology and shown to possess a timing jitter of 1.5 ns.
Abstract: This brief covers the design and fabrication of a ring oscillator-based truly random number generator (TRNG), which was fabricated in 013- $\mu\hbox{m}$ CMOS technology The randomness originates from the phase noise in a ring oscillator Timing jitter resulting from crossing the threshold multiple times, ie, last passage time (LPT), is exploited Previously, the jitter model was developed and applied to the core delay cell of the slow VCO, part of the ring oscillator, where a slow slew rate phase was introduced to greatly increase phase noise In this brief, the successful design of the entire TRNG was performed This includes designing the circuit to avoid introducing correlation in the TRNG Toward this end, novel timing circuitry is designed to properly control both the beginning and termination of this slow slew rate phase by tapping into the previous stage's output 1/f noise also has to be minimized Furthermore, the entire TRNG is now designed/implemented and fabricated, and experimental results are shown The fabricated ring oscillator was shown to possess a timing jitter of 15 ns Simulation under PVT variations of the entire cell shows that jitter variations are within 30%, showing that the designed control circuit was able to perform under such PVT variations Entropy simulation with power supply variations applied to the TRNG was also run to assess its effectiveness as the biasing condition is changing The randomness of the entire TRNG was assessed by applying the National Institute of Standards and Technology (NIST) tests On those tests recommended by NIST to have longer bit streams, additional test measurements were performed on bit streams with increased length Entropy tests for 20 k, 200 k, and 400 k measured bits were performed, resulting in entropy values all close to 1

56 citations

Patent
01 Nov 1988
TL;DR: In this article, an integrated circuit random number generator which uses a triangular output analog oscillator to vary the frequency of a higher frequency voltage controlled oscillator is presented. But the output of the voltage controlled OO is sampled at a rate much less than the rate of oscillation of the OO to produce random digital values.
Abstract: An integrated circuit random number generator which uses a triangular output analog oscillator to vary the frequency of a higher frequency voltage controlled oscillator. The output of the voltage controlled oscillator is sampled at a rate much less than the rate of oscillation of the voltage controlled oscillator to produce random digital values.

55 citations

Journal ArticleDOI
TL;DR: In this article, the authors presented a balanced voltage-controlled oscillator (VCO) monolithic microwave integrated circuits (MMICs) based on a coupled Colpitt topology with a fully integrated tank utilizing SiGe heterojunction bipolar transistor (HBT) and InGaP/GaAs HBT technologies.
Abstract: Balanced voltage-controlled oscillator (VCO) monolithic microwave integrated circuits (MMICs) based on a coupled Colpitt topology with a fully integrated tank are presented utilizing SiGe heterojunction bipolar transistor (HBT) and InGaP/GaAs HBT technologies. Minimum phase noise is obtained for all designs by optimization of the tank circuit including the varactor, maximizing the tank amplitude, and designing the VCO for Class C operation. Fundamental and second harmonic VCOs are evaluated. A minimum phase noise of less than -112 dBc at an output power of 5.5 dBm is achieved at 100-kHz carrier offset and 6.4-GHz oscillation frequency for the fundamental InGaP/GaAs HBT VCO. The second harmonic VCO achieves a minimum measured phase noise of -120 dBc at 100 kHz at 13 GHz. To our best knowledge, this is the lowest reported phase noise to date for a varactor-based VCO with a fully integrated tank. The fundamental frequency SiGe HBT oscillator achieves a phase noise of -108 dBc at 100 kHz at 5 GHz. All MMICs are fabricated in commercial foundry MMIC processes.

55 citations

Journal ArticleDOI
TL;DR: A fully integrated 40-Gb/s transceiver fabricated in a 0.13-mum CMOS technology performing half-rate clock and data recovery and a linear equalizer that tunes the resistive loading of an inductively-peaked CML buffer can improve the eye opening while operating at 39 Gb/s.
Abstract: A fully integrated 40-Gb/s transceiver fabricated in a 0.13-mum CMOS technology is presented. The receiver operates at a 20-GHz clock performing half-rate clock and data recovery. Despite the low fTof 70 GHz, the input sampler achieves 10-mV sensitivity using pulsed latches and inductive-peaking techniques. In order to minimize the feedback latency in the bang-bang controlled CDR loop, the proportional control is directly applied to the VCO, bypassing the charge pump and the loop filter. In addition, the phase detection logic operates at 20 GHz, eliminating the need for the deserializers for the early/late timing signals. The four clock phases for the half-rate CDR are generated by a quadrature LC-VCO with microstrip resonators. A linear equalizer that tunes the resistive loading of an inductively-peaked CML buffer can improve the eye opening by 20% while operating at 39 Gb/s. The prototype transceiver occupies 3.4 times 2.9 mm2 with power dissipation of 3.6 W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 215 -1 PRBS data is 1.85 psrms over a WB-PBGA package, an 8-mm PCB trace, an on-board 2.4-mm connector, and a 1 m-long 2.4-mm coaxial cable. The recovered divided-by-16 clock jitter is 1.77 psrms and the measured BER of the transceiver is less than 10- 14 .

55 citations

Journal ArticleDOI
TL;DR: In this paper, a closed-loop nonlinear simulation model for fractional-N synthesizers is presented, where an event-driven dual-iteration-based technique is used to generate a vector of piecewise linear time-voltage pairs, defining the voltage-controlled oscillator (VCO) control voltage.
Abstract: Wideband low-noise SigmaDelta fractional-N synthesizers pose several design challenges due to the nonlinear time-varying nature of synthesizer building blocks such as phase frequency detectors (PFDs), charge pump, and frequency dividers. Loop nonlinearities can increase close-in phase noise and enhance spurious tones due to intermodulation of high-frequency quantization noise and tonal content; therefore, an accurate simulation model is critical for successful implementation of loop parameters and bandwidth widening techniques. In this paper a closed-loop nonlinear simulation model for fractional-N synthesizers is presented. Inherent nonuniform sampling of the PFD is modeled through an event-driven dual-iteration-based technique. The proposed technique generates a vector of piecewise linear time-voltage pairs, defining the voltage-controlled oscillator (VCO) control voltage. This method also lends itself to modeling of cyclostationary thermal and flicker noise generated by time-varying charge-pump current pulses. A flexible third-order SigmaDelta modulated RF synthesizer core with integrated loop filter and LC-tank VCO is designed and fabricated in 0.13-mum CMOS process in order to validate the technique experimentally. The proposed modeling technique was able to predict in-band spur power levels with 1.8-dB accuracy, and spur frequency offsets with lower than 400-Hz accuracy with several programmable nonidealities enabled

55 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023168
2022344
2021269
2020388
2019469
2018530