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Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.


Papers
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Journal ArticleDOI
TL;DR: A novel single-chip 860–960MHz band UHF RFID reader transceiver IC is fabricated in 0.18µm CMOS technology and achieves IIP3 of 13dBm, sensitivity of −75dBm in listen-before-talk (LBT) mode and −66 dBm in normal mode in the presence of −4.4dBm self-jammer for the backscatter modulation while drawing 112mA from 3.3V power supply.
Abstract: UHF RFID reader transceiver for Chinese local standard (840-845 MHz and 920-925 MHz), in concord with the protocols of EPC Class-1 Gen-2 and ISO/IEC 18000-6C, is presented A highly linear RF front-end with low flicker noise, an on-chip self-jammer cancellation (SC) circuit with fast time-varying cut-off frequency and a DC-offset cancellation (DCOC) circuit are proposed to deal with the large self-jammer in the receiver In the presence of 22 dBm PA output power, the receiver achieves a sensitivity of -79 dBm including the 15 dB loss of the directional coupler A CMOS class-AB PA is integrated in the transmitter, with 22 dBm output power and 35% PAE The spectrum mask achieves ACPR1 of -45 dBc and ACPR2 of -60 dBc A sigma-delta fractional-N PLL with a single LC VCO is also implemented for good phase noise (-126 dBc/Hz @ 1 MHz offset) and high frequency resolution within 1 kHz This single-chip is fabricated in a 018 standard CMOS process It occupies a silicon area of 135 mm2 and dissipates 203 mW from a 18 V supply voltage when transmitting 75 dBm output power

55 citations

Journal ArticleDOI
TL;DR: In this paper, a low power, low phase noise 5.8 GHz voltage controlled oscillator (VCO) with on-chip CMOS MEMS inductor was fabricated by TSMC 0.18μm one-poly six-metal (1P6M) process and also Chip Implementation Center (CIC) micromachining post-process.
Abstract: This paper describes a low power, low phase noise 5.8 GHz voltage controlled oscillator (VCO) with on-chip CMOS MEMS inductor. The inductor was fabricated by TSMC 0.18 μm one-poly six-metal (1P6M) CMOS process and also Chip Implementation Center (CIC) micromachining post-process. During the post-process, the dry etching was utilized to remove the oxide between the winding metals and the silicon substrate under the inductor. Due to the alleviation of parasitic capacitance and lossy substrate, the quality factor and resonant frequency will be improved and extended. In this work, quality factor up to 15 was obtained for a 1.88 nH micromachined inductor at 8.5 GHz, and the improvement is up to 88% in maximum quality factor. The CMOS and micromachined inductor were both implemented with a 5.8 GHz VCO. Compared side by side with the CMOS inductor, the CMOS MEMS inductor produced a 5 dB lower phase noise improvement at 1 MHz offset in this 5.8 GHz VCO.

55 citations

Patent
20 Aug 2002
TL;DR: In this paper, a frequency synthesiser comprises a voltage controlled oscillator, VCO, having means for fine tuning the oscillator frequency and switchable capacitive elements for coarse tuning the frequency.
Abstract: A frequency synthesiser comprises a voltage controlled oscillator, VCO, having means for fine tuning the oscillator frequency and switchable capacitive elements for coarse tuning the oscillator frequency. First comparison means are provided for comparing the frequency and phase of the output of the VCO or a signal derived therefrom with that of a reference frequency signal to provide an error signal, the error signal being provided to said means for fine tuning the oscillator frequency. Second comparison means are provided for comparing the error signal against one or more reference values and a control means receives the result of the comparison from the second comparison means and switches said switchable capacitive elements on and off in dependence upon the result so as to coarse tune the oscillator frequency.

55 citations

Journal ArticleDOI
TL;DR: This paper introduces a continuous-time low-pass sigma-delta modulator operating with a seven-phase 400 MHz clocking scheme to control time-based processing in the 3-bit two-step quantizer and main digital-to-analog converter (DAC).
Abstract: This paper introduces a continuous-time low-pass sigma-delta modulator operating with a seven-phase 400 MHz clocking scheme to control time-based processing in the 3-bit two-step quantizer and main digital-to-analog converter (DAC). An on-chip voltage-controlled oscillator and a complementary injection-locked frequency divider are utilized for low-jitter clock signal generation with multiple phases, allowing 3-bit pulse-width modulated feedback with a single-element DAC to avoid performance degradation from unit element mismatch problems associated with conventional multi-bit DACs. Fabricated in a standard 0.18 μm CMOS technology, the 5th-order modulator achieves a peak SNDR of 67.7 dB in 25 MHz bandwidth, consumes 48 mW from a 1.8 V supply, and occupies a die area of 2.6 mm2. The modulator has a measured SFDR of 78 dB and in-band IM3 under -72 dB with -2 dBFS two-tone signal power.

55 citations

Journal ArticleDOI
TL;DR: The fractional frequency divider-by-1.25 can be used in a wireless transceiver to prevent direct or harmonic pulling of the VCO by the power amplifier and the low spur level facilitates radio co-existence with no need for additional filtering.
Abstract: This paper presents a fractional frequency divider-by-1.25 and associated all-digital calibration circuitry. The divider can be used in a wireless transceiver to prevent direct or harmonic pulling of the VCO by the power amplifier. Timing errors between the quadrature phases used in the phase-rotating divider introduce fractional spurs at the output. In this design, the timing errors are measured with a stochastic time-to-digital converter with 20 fs resolution, and corrected to suppress output spurs. The fractional divider has been implemented in a 45 nm CMOS LP process and its core dissipates an estimated 17 mA current from a 1.1 V supply. After calibration, fractional spurs are on average below -59 dBc and -50 dBc (? ~ 2 dB over 10 samples) with a 2.5 and 3.8 GHz output frequency respectively. Calibration performance has been confirmed for temperatures from -20°C up to 85°C. The low spur level facilitates radio co-existence with no need for additional filtering. This makes this divider a good candidate for WiFi and WiMAX radios up to 3.8 GHz.

55 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023168
2022344
2021269
2020388
2019469
2018530