Topic
Voltage-controlled oscillator
About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.
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Patent•
10 Aug 1987
TL;DR: In this paper, a random number generator designed for use with an electronic key uses a triangular output analog oscillator to vary the frequency of a higher frequency voltage controlled oscillator, which is sampled at a rate much less than the rate of oscillation of the voltage controlled OO to produce random digital values.
Abstract: A random number generator designed for use with an electronic key uses a triangular output analog oscillator to vary the frequency of a higher frequency voltage controlled oscillator. The output of the voltage controlled oscillator is sampled at a rate much less than the rate of oscillation of the voltage controlled oscillator to produce random digital values.
53 citations
01 Feb 2018
TL;DR: This work presents a quad-core bipolar VCO achieving phase noise as low as −124dBc/Hz at 1MHz offset from the 15GHz carrier, −189dBc /Hz figure-of-merit (FOM), and 16% tuning range, a key element in achieving the reported performance.
Abstract: The relentless development of next-generation communication and radar systems sets increasingly stringent requirements on the spectral purity of local oscillators. Decreasing phase noise is crucial to support efficient modulation formats with large symbol constellations, as well as to enable innovative radar applications, e.g., anti-collision, gesture recognition, and medical imaging. To minimize phase noise, bipolar transistors offer some advantages over ultra-scaled CMOS: higher supply voltage (thus larger oscillation amplitudes), lower 1/f noise, higher-Q passives (due to higher resistivity substrate and, possibly, thicker metals), and higher f T , f max for a given technology node, which results in a cost advantage for a variety of medium-volume applications (e.g., infrastructure transceivers). For a given supply voltage, a tank showing a smaller resistance at resonance yields lower phase noise. As a result, the minimum phase noise achievable by a single voltage-controlled oscillator (VCO) is ultimately bounded by the smaller realizable inductor displaying the highest Q. To achieve significantly lower phase noise levels, bilaterally coupling N oscillators [1-3] is a viable option. However, to fully preserve the 10log(N) phase-noise advantage, while avoiding undesired multi-tone concurrent oscillations, the coupling network must be carefully designed. This work presents a quad-core bipolar VCO achieving phase noise as low as −124dBc/Hz at 1MHz offset from the 15GHz carrier, −189dBc/Hz figure-of-merit (FOM), and 16% tuning range. Insights are given into the design of the resistive network employed to couple the four oscillators, a key element in achieving the reported performance.
53 citations
TL;DR: In this article, a fully integrated complementary metal oxide semiconductor (CMOS) cascode LC voltage controlled oscillator (VCO) with Q-enhancement technique has been designed for high frequency and low phase noise.
Abstract: A fully integrated complementary metal oxide semiconductor (CMOS) cascode LC voltage controlled oscillator (VCO) with Q-enhancement technique has been designed for high frequency and low phase noise. The symmetrical cascode architecture is implemented with negative conductance circuit for improving phase noise performance in 0.18 mum CMOS technology. The measured phase noise is -110.8 dBc/Hz at the offset frequency of 1 MHz. The tuning range of 630 MHz is achieved with the control voltage from 0.6 to 1.4 V. The VCO draws 4.5 mA in a differential core circuit from 1.8 V supply.
53 citations
16 Feb 1994
TL;DR: In this article, a monolithic integrated silicon bipolar circuit can provide phase and frequency locked loop (PFLL) based clock recovery and data regeneration up to 8Gb/s with an external VCO.
Abstract: This contribution shows that a monolithic integrated silicon bipolar circuit can provide phase and frequency locked loop (PFLL) based clock recovery and data regeneration up to 8Gb/s. Moreover, phase and frequency detector (PFD) operation up to 15Gb/s (with an external VCO) is demonstrated. Owing to the wide tuning range of the quadrature VCO, the circuit lends itself to operation over a wide range of bit rates. Other applications of the quadrature VCO, e.g. as a synthesizer, are possible. As shown by circuit simulations, the operating frequency can be extended beyond 1OGHz, if a small unbalance between both ring oscillator stages is eliminated by minor design changes. >
53 citations
Patent•
31 Oct 1986TL;DR: In this article, the reference oscillator (21) is controlled in closed loop manner through use of a phase-locked loop that responds, in part, to the lock frequency of the FM detector phase locked loop.
Abstract: A reference oscillator (21) suitable for use in a radio transceiver having a phase locked loop FM detector (12). During normal reception operation, the reference oscillator (21) can be controlled in closed loop manner through use of a phase locked loop that responds, in part, to the lock frequency of the FM detector phase locked loop. During transmit functions, or during other periods when the closed loop control may not provide accurate reference oscillator (21) operation, open loop control can be provided instead. Open loop control includes use of a stored value that reflects a most recent reliable value of an appropriate input control signal for the reference oscillator (21).
52 citations