Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.

Phase-locked loop frequency tracking device including a direct digital synthesizer

Abstract: Disclosed is a single phase-locked loop (50, 350) providing tuning over a very large bandwidth for use in wide band carrier tracking and clock recovery systems. In a first embodiment, a DC signal is formed representative of a phase difference between an input signal changing with time and a return signal. The DC signal is applied to a narrow band voltage controlled oscillator (68) which converts the DC signal back to an AC signal. The AC signal is level shifted to form a clocking pulse for an accumulator (80) of a direct digital synthesizer (72). A digital command word is also applied to the accumulator (80), such that the digital command word represents a coarse tuning of the input frequency. The clocking pulse from the narrow band VCO (68) supplies a fine tuning of the input frequency. In a second embodiment, the DC representative phase signal is applied to an analog-to-digital converter (364) which produces an N-bit word representative of the phase difference. The change in phase alters the digital output of the analog-to-digital converter (364) which in turn is applied to the accumulator (376) of a direct digital synthesizer (370). By this invention, very wide band tracking is capable with a single phase-locked loop, thus limiting the hardware and cost.

Dual phase-locked-loop having forced mid range fine control zero at handover

Abstract: Method and apparatus for controlling a PLL so that handover between fine and coarse loops take place at 2.5% of the nominal VCO frequency and where the coarse and fine loops error are combined in a summer circuit which employs a series circuit having a P-channel and N-channel FET with common drains and where the drains connected to the summer output node.

Variable-Frequency Fluidic Oscillator Driven by a Piezoelectric Bender

Abstract: §This paper describes a new actuator for flow control applications ‐ the piezo-fluidic oscillator. The actuator is a fluidic device based on wall-attachment of a fluid jet, and modulated by piezoelectric devices. The piezo-fluidic oscillator successfully decouples the operating frequency from the flow characteristics of the device. The frequency is specified by an input electrical signal that is independent of pressure, making this actuator ideal for closed-loop control applications. The oscillator exhibits high bandwidth (up to 1.2 kHz), modulation rates up to 100%, and a velocity range reaching sonic conditions. Furthermore, the bi-stable actuator may be operated in a steady state, with momentum flux in one of two desired directions. The piezo-fluidic oscillator may be used in flow control applications where synthetic jets cannot provide enough momentum for control authority. The actuator can also be used as an alternative to traditional aircraft control surfaces while operating in the steady bi-directional mode. This paper details the design and characterization of the piezo-fluidic oscillator. The dynamic response characteristics are evaluated with flow visualization and hot film probe measurements on the output. **

A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation

Abstract: We present an analog subsampling PLL based on a digital-to-time converter (DTC), which operates with almost no performance gap (176/198 fs RMS jitter) between the integer and the worst case fractional operation, achieving −246.6 dB FOM in the worst case fractional mode. The PLL is capable of two-point, 10 Mbit/s GMSK modulation with −40.5 dB EVM around a 10.24 GHz fractional carrier. The analog nonidealities—DTC gain, DTC nonlinearity, modulating VCO bank gain, and nonlinearity—are calibrated in the background while the system operates normally. This results in ~15 dB fractional spur improvement (from −41 dBc to −56.5 dBc) during synthesis and ~15 dB EVM improvement (from −25 dB to −40.5 dB) during modulation. The paper provides an overview of the mechanisms that contribute to performance degradation in DTC-based PLL/phase modulators and presents ways to mitigate them. We demonstrate state-of-the-art performance in nanoscale CMOS for fractional-N synthesis and phase modulation.

Parasitic-Aware Optimization of CMOS RF Circuits

Abstract: Dedication. Contributing Authors. Preface. Part I: Background on Parasitic-Aware Optimization. 1: Introduction. 1. Introduction. 2. Overview of Wireless Transceivers. 3. Outline of the Book. 2: Modeling of On-Chip Passive and Active Components. 1. Monolithic Inductors. 2. Monolithic Varactors. 3. MOS Transistors. 3: Parasitic-Aware Optimization. 1. Gradient Decent Optimization. 2. Simulated Annealing. 3. Simulated Annealing with Tunneling Process. 4. Genetic Algorithm (GA). 5. Particle Swarm Optimization (PSO). 6. Post PVT Variation Optimization. Part II: Optimization of CMOS RF Circuits. 4: Optimization of CMOS Low Noise Amplifiers. 1. Low Noise Amplifier. 2. Design of Low Noise Amplifier. 3. Optimization of Low Noise Amplifiers. 5: Optimization of CMOS Mixers. 1. Mixer. 2. Single Balanced Mixer. 3. Double Balanced Mixer. 4. Design of Mixers. 5. Optimization of Mixers. 6: Optimization of CMOS Oscillators. 1. CMOS Oscillators. 2. Phase Noise. 3. Design of VCO. 4. Optimization of CMOS VCO. 7: Optimization of CMOS RF Power Amplifiers. 1. RF Power Amplifiers. 2. Design of Power Amplifier. 3. Optimization of Power Amplifier. 4.POST PVT Optimization. 8: Optimization of Ultra-Wideband Amplifiers. 1. CMOS Ultra-Wideband Amplifiers. 2. Design of CMOS Ultra-Wideband Amplifier. 3. Optimization of CMOS Ultra-Wideband Amplifier. Index.