Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.

An 18-mW 1.175–2-GHz Frequency Synthesizer With Constant Bandwidth for DVB-T Tuners

Abstract: A fully integrated 1.175-2-GHz differentially tuned frequency synthesizer aimed for digital video broadcasting-terrestrial tuners is implemented in a 0.18-mum CMOS process. To maintain phase-noise optimization and loop stability over the entire output frequency range, techniques of constant loop bandwidth are proposed. The voltage-controlled oscillator gain K VCO and band step f res are both maintained by simultaneously adjusting the sizes of switched capacitors and varactors. Charge pump current I CP is programmed to compensate the variation of the division ratio N . The measured results show an in-band phase noise of -97.6 dBc/Hz at a 10-kHz offset and an integrated phase error of 0.63 deg from 100 Hz to 10 MHz. The measured variations of K VCO and f res are less than 12.5% and 4.5%, respectively. The variations of the measured phase noise at 10-kHz and 1-MHz frequency offsets are less than 1 dB. The measured 3-dB closed-loop bandwidth is 110 kHz and the variation is less than 9%. The chip draws 10-mA current from a 1.8-V supply while occupying a 2.2-mm2 die area.

A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18-/spl mu/m CMOS process

Abstract: A 1-V 24-GHz 17.5-mW fully integrated phase-locked loop employing a transformer-feedback voltage-controlled oscillator and a stacked divide-by-2 frequency divider for low voltage and low power is presented. Implemented in a 0.18-/spl mu/m CMOS process and operated at 24 GHz with a 1-V supply, the PLL measures in-band phase noise of -106.3 dBc at a frequency offset of 100 kHz and out-of-band phase noise of -119.1 dBc/Hz at a frequency offset of 10 MHz. The PLL dissipates 17.5 mW and occupies a core area of 0.55 mm/sup 2/.

Bit phase synchronizing circuitry for controlling phase and frequency, and PLL circuit therefor

Abstract: In bit phase synchronizing circuitry, received data with an unknown phase and triphase clocks output from a reset VCO (Voltage Controlled Oscillator) are input to a timing decision circuit. If preselected one of the triphase clocks and the received data have an adequate relation, the decision circuit causes the current clock phase to be maintained. If otherwise, the decision circuit determines whether the current clock phase should be advanced or retarded. The resulting decision signal output from the decision circuit is fed to a selector controller. The decision circuit latches the received data with the preselected one of the triphase clocks and outputs them together with the clock used for latching. A phase controller causes the reset VCO to selectively operate in a phase shift mode or in a multiplication PLL (Phase Locked Loop) mode. The circuitry is capable of setting up bit phase synchronization stably and rapidly with a simple configuration without regard to the phase of the received data. In addition, the circuitry is little susceptible to noise.

A W-band single-chip transceiver for FMCW radar

Abstract: A monolithic microwave integrated circuit (MMIC) chip containing a W-band voltage controlled oscillator (VCO). transmit amplifiers, a receiver low noise amplifier and a mixer is discussed. It is used as the front-end of a homodyne FMCW radar for target range and range rate sensing applications. The 6.9-mm*3.6-mm monolithic chip was fabricated using 0.1- mu m pseudomorphic InGaAs-AlGaAs-GaAs HEMT process technology. The transmitter output power is more than 10 dBm for frequencies in the range 90-94 GHz, and maximum tuning bandwidth is 500 MHz for the VO. The receiver channel has 6-dB conversion gain when the output transmitting power is 10 dBm. A compete radar system has been tested based on the single-chip MMIC front-end. The calculated range and range rate are in good agreement with the measurement data. >

A GSM-GPRS/UMTS FDD-TDD/WLAN 802.11a-b-g multi-standard carrier generation system

Abstract: A compact carrier generation system enabling proper interoperability among quad-band GSM, WCDMA (FDD and TDD), and WLAN (802.11a/b/g) standards is developed. The implementation is achieved in 0.25-mum BiCMOS-SiGe process. The measured tuning range is higher that 1 GHz (3.05 to 4.1 GHz) exceeding the specifications by 25%. The voltage-controlled oscillator (VCO) exhibits a phase noise of -118 and -125 dBc/Hz measured, respectively, at 400 kHz and 1 MHz offsets while drawing 2.5 mA from 2.5 V supply. The measured phase noise at 400 kHz offset of the PCS/DCS output local-oscillator (LO) signal and the GSM output LO signal is, respectively, -124 dBc/Hz and -130 dBc/Hz