Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.

Data dejittering apparatus

Abstract: A circuit for dejittering transmitted digital data. A buffer stores the incoming data and has its half-full condition monitored by content decoding circuitry including a counter whose count is converted to control the frequency of a voltage controlled oscillator. The oscillator clocks the data out of the buffer effectively free of harmful jitter.

Lock recovery circuit for a phase locked loop

Abstract: A circuit (10) for providing recovery of a phase locked loop circuit when lock has been lost has been provided. The circuit includes a lock indicator circuit (24) for detecting when the phase locked loop circuit has lost lock on an input reference signal. When such loss has occurred, an override circuit (28) is rendered operative to decrease the voltage appearing at the input of a VCO within the phase locked loop thereby slowing down the frequency of the VCO and allowing the phase locked loop circuit to recover lock. Further, a logic circuit (30) detects when the voltage appearing at the input of the VCO has fallen below a predetermined threshold voltage and renders the override circuit non-operative.

Computer based fast phase difference measuring unit and PLL using same

Abstract: A system for measuring a phase difference between two input signals, including a computer performing computations in the complex domain and operating on two complex signals indicative of the two input signals respectively to compute the phase difference. Alternately, the system for measuring the phase difference includes a computer operating on two input buses indicative of the two input signals respectively to generate a signal indicative of the phase difference, and wherein: A. each input bus includes at least two digital bits; B. the two input buses are indicative of the phase of each of the two input signals; C. the two input buses each has a different range of possible values and wherein the computer further includes a device for normalizing at least one of the buses so as to bring the two buses to the same range. A phase-lock loop includes the system for measuring the phase difference, a VCO and digital devices.

Direct digital frequency synthesis enabling spur elimination

Abstract: The present invention, generally speaking, provides improved methods of generating clean, precisely-modulated waveforms, at least partly using digital techniques. In accordance with one aspect of the invention, a 'difference engine' is provided that produces a digital signal representing the frequency error between a numeric frequency and an analog frequency. The frequency error may be digitally integrated to produce a digital signal representing the phase error. The difference engine may be incorporated into a PLL, where the analog frequency is that of an output signal of a VCO of the PLL. Direct modulation of the PLL output signal may be performed numerically. By further providing an auxiliary modulation path and performing calibration between the direction modulation path and the auxiliary modulation path, modulation characteristics may be separated from loop bandwidth constraints. In particular, the loop bandwidth of the PLL may be made so low as to reduce spurs (usually associated with DDS techniques) to an arbitrarily low level. A loop filter of the PLL may be realized in digital form. Using a digital loop filter would ordinarily require use of a high-resolution DAC. Various techniques are described for reducing the resolution requirements of the DAC.

Comparison frequency doubling and charge pump matching techniques for dual-band /spl Delta//spl Sigma/ fractional-N frequency synthesizer

Abstract: The frequency synthesizer with two LC-VCOs is fully integrated in a 0.35-/spl mu/m CMOS technology. In supporting dual bands, all building blocks except VCOs are shared. A current compensation scheme using a replica charge pump improves the linearity of the frequency synthesizer and, thus, suppresses spurious tones. To reduce the quantization noise from a /spl Delta//spl Sigma/ modulator and the noise from the building blocks except the VCO, the proposed architecture uses a frequency doubler with a noise-insensitive duty-cycle correction circuit (DCC) in the reference clock path. Power consumption is 37.8 mW with a 2.7-V supply. The proposed frequency synthesizer supports 10-kHz channel spacing with the measured phase noise of -114 dBc/Hz and -141 dBc/Hz at 100-kHz and 1.25-MHz offsets, respectively, in the PCS band. The fractional spurious tone at 10-kHz offset is under -54 dBc.