Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.

A 6 GHz 68 mW BiCMOS phase-locked loop

Abstract: The design of a 6 GHz fully monolithic phase-locked loop fabricated in a 1 /spl mu/m, 20 GHz BiCMOS technology is described. The circuit incorporates a voltage-controlled oscillator that senses and combines the transitions in a ring oscillator to achieve a period equal to two ECL gate delays. A mixer topology is also used that exhibits full symmetry with respect to its inputs and operates with supply voltages as low as 1.5 V. Dissipating 60 mW from a 2 V supply, the circuit has a tracking range of 300 MHz, an rms jitter of 3.1 ps, and phase noise of -75 dBc/Hz at 1 kHz offset. >

Wideband VCO with Simultaneous Switching of Frequency Band, Active Core and Varactor Size

Abstract: As the tuning range of integrated LC VCOs increases, it becomes difficult to co-design the active negative resistance core and the varactor optimally for the complete frequency range. The VCO presented here solves this by adjusting the negative resistance with a switched active core. Also the VCO gain variations are counteracted by employing an analog varactor that can change in size. The implementation in 0.13mum CMOS shows a tuning range from 3.1 to 5.2 GHz, with a power consumption varying accordingly from 2.1 to 7.7 mA from a 1.2V supply. The measured phase noise is -118 dBc at 1 MHz from a 4-GHz carrier

Method and apparatus for generating random numbers

Abstract: A random number generator generates high quality random numbers by sampling the output of a voltage controlled oscillator (VCO) at a frequency much lower than the frequency of the oscillator output. The output frequency of the oscillator is changed significantly during each sampling interval to help ensure the phase relationship of the VCO output and the sampling frequency is unpredictable. That may be accomplished by logically combing the sampling clock and an output from a linear feedback shift register in an exclusive OR gate and supplying that output as the most significant bit used to generate the voltage to control the oscillator. Additional outputs from the linear feedback shift register are also used to generate the control input to the VCO. A distilling circuit such as a CRC circuit or a linear feedback shift register shifts in successive output samples and generates a number therefrom to further increase the randomness of the generated random number.

A Low Voltage Divide-by-4 Injection Locked Frequency Divider With Quadrature Outputs

Abstract: This letter presents a low voltage quadrature divide-by-4 (divide4) injection-locked frequency divider (QILFD). The QILFD consists of a 1.8-GHz quadrature voltage controlled oscillator (QVCO) and two NMOS switches, which are inserted into the quadrature outputs of the QVCO for signal injection. The low-voltage CMOS divide4 QILFD has been implemented with the TSMC 0.18-mum 1P6 M CMOS technology and the core power consumption is 3.12mW at the supply voltage of 1.2V. The free-running frequency of the QILFD is tunable from 1.73 to 1.99GHz, the measured phase noise of QILFD is -118dBc/Hz at 1-MHz offset from the free running frequency of 1.82GHz. At the input power of 0dBm, the total locking range is from 6.86 to 8.02GHz as the tuning voltage is varied from 0 to 1.2V. The phase noise of the locked output spectrum is lower than that of free running ring oscillator by 11dBc/Hz. The phase deviation of quadrature output is about 0.8deg

A 1.8-GHz injection-locked quadrature CMOS VCO with low phase noise and high phase accuracy

Abstract: Injection-locked quadrature voltage-controlled oscillators are introduced in this paper as high accuracy, low phase noise, and low-power I and Q generators. A master voltage-controlled oscillator (VCO), running at twice the output frequency, locks two coupled VCOs. The former determines phase noise while the latter sets phase accuracy, thus, breaking the tradeoff between the two parameters, the main limit of free running coupled VCOs, recently proposed in the framework of highly integrated solutions. The proposed design has been tailored to DCS 1800 and prototypes have been fabricated in a 0.18-mum CMOS technology. Experiments show a phase noise of -127 dBc/Hz and -139 dBc/Hz at 600 kHz and 3 MHz, respectively, while consuming 10 mA from 1.8 V supply. A 185-dB state-of-the-art phase noise figure of merit results. Accuracy between output signals is determined by means of image band rejection (IBR) measurements on a purposely developed single-side-band upconversion mixer. Minimum IBR among 20 samples is as large as 46 dB