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Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.


Papers
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Proceedings ArticleDOI
Yves Baeyens1, Young-Kai Chen1
08 Jun 2003
TL;DR: In this paper, a push-push voltage controlled oscillator (VCO) with simultaneous differential output is realized using an advanced 0.13/spl mu/m SiGe HBT process.
Abstract: A fully integrated push-push voltage controlled oscillator (VCO) with simultaneous differential fundamental output is realized using an advanced 0.13/spl mu/m SiGe HBT process. A maximum oscillation frequency of 155 GHz, up to -5 dBm output power at 150 GHz and 30 GHz wide tuning range is achieved. The measured phase-noise in the linear tuning range is around -85 dBc/Hz at 1 MHz offset from carrier. Up to +3 dBm output power and 6 dB lower phase noise is obtained at each of the fundamental frequency differential ports. For a similar but fixed frequency oscillator, -2 dBm output power and a low phase noise of less than -90 dBc/Hz is measured at 1 MHz from the 140 GHz carrier.

47 citations

Proceedings ArticleDOI
28 Mar 2013
TL;DR: A dual-loop topology with one free-running voltage-controlled oscillator (VCO) as a replica VCO placed inside a FLL for tracking temperature and voltage drift is proposed, which provides robust output over temperature and Voltage variations.
Abstract: For modern SoC systems, stringent requirements on on-chip clock generators include low area, low power consumption, environmental insensitivity, and the lowest possible jitter performance. Multiplying Delay-Locked Loop (MDLL) [1-2], subharmonically injection-locked techniques [3], and sub-sampling techniques [4-5] can significantly improve the random jitter characteristics of a clock generator. However, in order to guarantee their correct operation and optimal performance over process-voltage-temperature (PVT) variations, each method requires additional calibration circuits, which impose difficult-to-meet timing constraints. In the case of an injection-locked PLL (IL-PLL), a free-running frequency calibration is required. However, the output of an injection-locked oscillator is always fixed at the desired frequency, so a shift in the free-running frequency (e.g. caused by temperature and voltage variations) cannot be simply compensated for by using a frequency-locked loop (FLL). Therefore, we propose the use of a dual-loop topology with one free-running voltage-controlled oscillator (VCO) as a replica VCO placed inside a FLL for tracking temperature and voltage drift. The other VCO (the main VCO) is injection locked for producing a low-jitter clock, while the free-running frequency shift can be compensated for by the replica loop. The method provides robust output over temperature and voltage variations.

47 citations

Proceedings ArticleDOI
22 Nov 2004
TL;DR: A model for the hand analysis of VCO noise is presented giving excellent agreement with measurements, and an integrated regulator provides low supply pushing, reduces AM-to-PM sensitivity from the supply, and ensures optimum operation on multi-band/multi-standard single-chip transceivers with simultaneous operation.
Abstract: This paper presents a CMOS VCO in a 0.35 /spl mu/m process which achieves a tuning range of 2.8 GHz-4.55 GHz and phase noise of -142dBc/Hz at 3 MHz offset (from a 1.8 GHz carrier). 5-bit digital coarse-tuning and accumulation-type MOS varactors allow for a 48% tuning range. An integrated regulator provides low supply pushing (100 kHz/V), reduces AM-to-PM sensitivity from the supply, and ensures optimum operation on multi-band/multi-standard single-chip transceivers with simultaneous operation. A model for the hand analysis of VCO noise is presented giving excellent agreement with measurements.

47 citations

Journal ArticleDOI
TL;DR: In this article, a 1-V CMOS frequency synthesizer designed for WLAN 802.11a is presented, which measures phase noise of -136 dBc/Hz at a frequency offset of 20 MHz and spur performance of less than -80 dBc at an offset of 11 MHz.
Abstract: A 1-V CMOS frequency synthesizer designed for WLAN 802.11a is presented. Novel circuit designs are demonstrated in the system for low-voltage applications including design of voltage-controlled oscillator and design of programmable divider. Implemented in a 0.18-/spl mu/m CMOS process and operated at 1-V supply voltage, the synthesizer measures phase noise of -136 dBc/Hz at a frequency offset of 20 MHz and spur performance of less than -80 dBc at an offset of 11 MHz. The synthesizer dissipates 27.5 mW from a single 1-V supply and occupies a chip area of 1.03 mm/sup 2/.

47 citations

Proceedings ArticleDOI
01 Feb 2008
TL;DR: A differential CMOS Colpitts oscillator directly derived from a singled-ended topology did not show a better phase noise performance than the conventional CMOS differential-pair LC-tank oscillator, not even theoretically.
Abstract: Colpitts oscillators have long been known for their excellent phase-noise properties; yet, a differential CMOS Colpitts oscillator, directly derived from a singled-ended topology, did not show a better phase noise performance than the conventional CMOS differential-pair LC-tank oscillator, not even theoretically (Andreani, 2005).

47 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023168
2022344
2021269
2020388
2019469
2018530