Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.

Digital-to-analog converter circuit incorporating hybrid sigma-delta modulator circuit

Abstract: An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. A multiplexer is configured to respectively convey the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. Each of the DACs preferably includes a hybrid first order/second order sigma-delta modulator, and in certain embodiments, a NRZ-to-RZ coder circuit, and a linear filter circuit.

Noise shaping techniques for analog and time to digital converters using voltage controlled oscillators

Abstract: Advanced CMOS processes offer very fast switching speed and high transistor density that can be utilized to implement analog signal processing functions in interesting and unconventional ways, for example by leveraging time as a signal domain. In this context, voltage controlled ring oscillators are circuit elements that are not only very attractive due to their highly digital implementation which takes advantage of scaling, but also due to their ability to amplify or integrate conventional voltage signals into the time domain. In this work, we take advantage of voltage controlled oscillators to implement analogand time-to-digital converters with first-order quantization and mismatch noise-shaping. To implement a time-to-digital converter (TDC) with noise-shaping, we present a oscillator that is enabled during the measurement of an input, and then disabled in between measurements. By holding the state of the oscillator in between samples, the quantization error is saved and transferred to the following sample, which can be seen as first-order noise-shaping in the frequency domain. In order to achieve good noiseshaping performance, we also present key details of a multi-path oscillator topology that is able to reduce the effective delay per stage by a factor of 5 and accurately preserve the quantization error from measurement to measurement. An 11-bit, 50Msps prototype time-to-digital converter (TDC) using a multi-path gated ring oscillator with 6ps of delay per stage demonstrates over 20dB of 1st-order noise shaping. At frequencies below 1MHz, the TDC error integrates to 80fsrms for a dynamic range of 95dB with no calibration of differential non-linearity required. The 157x258μm TDC is realized in 0.13μm CMOS and operates from a 1.5V supply. The use of VCO-based quantization within continuous-time (CT) Σ∆ ADC structures is also explored, with a custom prototype in 0.13μm CMOS showing measured performance of 86/72dB SNR/SNDR with 10MHz bandwidth while consuming 40mW from a 1.2V supply and occupying an active area of 640μm X 660μm. A key element of the ADC structure is a 5-bit VCO-based quantizer clocked at 950 MHz which we show achieves first-order noise-shaping of its quantization noise. The quantizer structure allows the second order CT Σ∆ ADC topology to achieve third order noise 3 shaping, and direct connection of the VCO-based quantizer to the internal DACs of the ADC provides intrinsic dynamic element matching (DEM) of the DAC elements. Thesis Supervisor: Michael H. Perrott Title: Associate Professor

Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise

Abstract: Phase-locked loops (PLLs) are widely used in electronic systems. As PLL malfunction is one of the most important factors in re-fabs of SoCs, fast simulation of PLLs to capture non-ideal behavior accurately is an immediate, pressing need in the semiconductor design industry. In this paper, we present a nonlinear macro model based PLL simulation technique that is considerably more accurate than prior linear PLL simulation techniques. Our method is able to accurately capture transient behavior and faithfully estimate timing jitter in noisy PLLs. We demonstrate the proposed technique on ring and LC voltage-controlled oscillator (VCO) based PLLs, and compare results against linear PLL macromodels and full SPICE-level simulation. We show that, unlike prior linear macromodel based approaches, the proposed nonlinear technique captures the dynamics of complex phenomena such as locking, cycle slipping and power supply noise induced PLL jitter, replicating qualitative features from full SPICE simulations accurately while providing speedups of over two orders of magnitude.

Panoramic time delay and integration video camera system

Abstract: One or more time delay and integration camera assemblies (A) are mounted in a housing (100) which is rotated by a motor (40, 106) relative to a vertical axis. A tachometer or encoder (44) produces signals whose frequency or voltage varies in accordance with an angular velocity of the camera assemblies about the vertical axis. A clock generator (46) converts the angular velocity signals into clocking signals for controlling movement of vertical lines of data values (20) along an array (14) of light sensitive elements to a shift register (22). In one embodiment, the clock generator includes a divider (82) which converts the angular velocity signal into a voltage, a comparator (84) which compares the first voltage with a second voltage, and a voltage controlled oscillator (88) which oscillates to generate the clocking signal. A second divider (88) defines a feedback loop between the output of the voltage controlled oscillator and the comparator for generating the second voltage. Each line of data from the array update (64) a corresponding line of a panoramic memory (66). The selectable portion (72) of the data from the panoramic memory is retrieved (70) independently of the memory updating. Scan converters (74) convert retrieved portions of the panoramic memory data into appropriate format for display on video monitor (78). In this manner, the panoramic memory is updated as the array rotates and data is independently retrieved from the panoramic memory to form panable displays.

Integrated Inductors for RF Transmitters in CMOS/MEMS Smart Microsensor Systems

Abstract: This paper presents the integration of an inductor by complementary metal-oxide-semiconductor (CMOS) compatible processes for integrated smart microsensorsystems that have been developed to monitor the motion and vital signs of humans invarious environments. Integration of radio frequency transmitter (RF) technology withcomplementary metal-oxide-semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize the wireless smart microsensors system. Theessential RF components such as a voltage controlled RF-CMOS oscillator (VCO), spiralinductors for an LC resonator and an integrated antenna have been fabricated and evaluatedexperimentally. The fabricated RF transmitter and integrated antenna were packaged withsubminiature series A (SMA) connectors, respectively. For the impedance (50 ) matching,a bonding wire type inductor was developed. In this paper, the design and fabrication of thebonding wire inductor for impedance matching is described. Integrated techniques for theRF transmitter by CMOS compatible processes have been successfully developed. Aftermatching by inserting the bonding wire inductor between the on-chip integrated antennaand the VCO output, the measured emission power at distance of 5 m from RF transmitterwas -37 dBm (0.2 μW).