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Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.


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08 Dec 2008
TL;DR: Noise in delay-line oscillators and lasers, phase noise and frequency stability, and Oscillator hacking A Laplace transform.
Abstract: Foreword Lute Maleki Foreword David B. Leeson Preface List of symbols 1. Phase noise and frequency stability 2. Phase noise in semiconductors and amplifiers 3. Heuristic approach to the Leeson effect 4. Phase noise and linear feedback theory 5. Noise in delay-line oscillators and lasers 6. Oscillator hacking A Laplace transform Bibliography.

406 citations

Journal ArticleDOI
TL;DR: A general theory that allows the accurate linear and nonlinear analysis of any crystal oscillator circuit is presented and a 2-MHz CMOS oscillator which uses amplitude stabilization to minimize power consumption and to eliminate the effects of nonlinearities on frequency is described.
Abstract: A general theory that allows the accurate linear and nonlinear analysis of any crystal oscillator circuit is presented. It is based on the high Q of the resonator and on a very few nonlimiting assumptions. The special case of the three-point oscillator, that includes Peirce and one-pin circuits, is analyzed in more detail. A clear insight into the linear behavior, including the effect of losses, is obtained by means of the circular locus of the circuit impedance. A basic condition for oscillation and simple analytic expressions are derived in the lossless case for frequency pulling, critical transconductance, and start-up time constant. The effects of nonlinearities on amplitude and on frequency stability are analyzed. As an application, a 2-MHz CMOS oscillator which uses amplitude stabilization to minimize power consumption and to eliminate the effects of nonlinearities on frequency is described. The chip, implemented in a 3- mu m p-well low-voltage process, includes a three-stage frequency divider and consumes 0.9 mu A at 1.5 V. The measured frequency stability is 0.05 p.p.m./V in the range 1.1-5 V of supply voltage. Temperature effect on the circuit itself is less than 0.1 p.p.m. from -10 to +60 degrees C. >

385 citations

Journal ArticleDOI
TL;DR: The use of VCO-based quantization within continuous-time (CT) SigmaDelta analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 mum CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth.
Abstract: The use of VCO-based quantization within continuous-time (CT) SigmaDelta analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 mum CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth while consuming 40 mW from a 1.2 V supply and occupying an active area of 640 mum times 660 mum. A key element of the ADC structure is a 5-bit VCO-based quantizer clocked at 950 MHz which achieves first-order noise shaping of its quantization noise. The quantizer structure allows the second-order CT SigmaDelta ADC topology to achieve third-order noise shaping, and direct connection of the VCO-based quantizer to the internal DACs of the ADC provides intrinsic dynamic element matching of the DAC elements.

350 citations

Journal ArticleDOI
TL;DR: In this article, a 1.8 GHz LC VCO designed in a 0.18-/spl mu/m CMOS process achieves a very wide tuning range of 73% and measured phase noise of -123.5 dBc/Hz at a 600-kHz offset from a 1 8 GHz carrier while drawing 3.2 mA from a 3.5-V supply.
Abstract: A 1.8-GHz LC VCO designed in a 0.18-/spl mu/m CMOS process achieves a very wide tuning range of 73% and measured phase noise of -123.5 dBc/Hz at a 600-kHz offset from a 1.8-GHz carrier while drawing 3.2 mA from a 1.5-V supply. The impacts of wideband operation on start-up constraints and phase noise are discussed. Tuning range is analyzed in terms of fundamental dimensionless design parameters yielding useful design equations. An amplitude calibration technique is used to stabilize performance across the wide band of operation. This amplitude control scheme not only consumes negligible power and area without degrading the phase noise, but also proves to be instrumental in sustaining the VCO performance in the upper end of the frequency range.

348 citations

Journal ArticleDOI
TL;DR: A major contribution is the identification of a design figure of merit /spl kappa/, which is independent of the number of stages in the ring, used to relate fundamental circuit-level noise sources (such as thermal and shot noise) to system-level jitter performance.
Abstract: Jitter in ring oscillators is theoretically described, and predictions are experimentally verified. A design procedure is developed in the context of time domain measures of oscillator jitter in a phase-locked loop (PLL). A major contribution is the identification of a design figure of merit /spl kappa/, which is independent of the number of stages in the ring. This figure of merit is used to relate fundamental circuit-level noise sources (such as thermal and shot noise) to system-level jitter performance. The procedure is applied to a ring oscillator composed of bipolar differential pair delay stages. The theoretical predictions are tested on 155 and 622 MHz clock-recovery PLL's which have been fabricated in a dielectrically isolated, complementary bipolar process. The measured closed-loop jitter is within 10% of the design procedure prediction.

328 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023168
2022344
2021269
2020388
2019469
2018530