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Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.


Papers
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Journal ArticleDOI
TL;DR: Compared with the commonly used class-B/C architectures, the optimal class-D oscillator produces less phase noise for the same power consumption, at the expense of a higher power supply pushing.
Abstract: This paper presents class-D CMOS oscillators capable of an excellent phase noise performance from a very low power supply voltage. Starting from the recognition of the time-variant nature of the class-D LC tank, accurate expressions of the oscillation frequency, oscillation amplitude, current consumption, phase noise, and figure-of-merit (FoM) have been derived. Compared with the commonly used class-B/C architectures, the optimal class-D oscillator produces less phase noise for the same power consumption, at the expense of a higher power supply pushing. A prototype of a class-D voltage-controlled oscillator (VCO) targeted for mobile applications, implemented in a standard 65-nm CMOS process, covers a 46% tuning range between 3.0 and 4.8 GHz; drawing 10 mA from 0.4 V, the phase noise at 10-MHz offset from 4.8 GHz is -143.5 dBc/Hz, for an FoM of 191 dBc/Hz with less than 1-dB variation across the tuning range. A version of the same VCO with a resonant tail filter displays a lower 1/f3 phase-noise corner and improves the FoM by 1 dB.

128 citations

Patent
19 Jun 1997
TL;DR: In this paper, a parallel sampling phase detector with linear output response was proposed for data recovery, which includes a voltage controlled oscillator (VCO) that generates ten separate phase signals using a five stage ring oscillator.
Abstract: A parallel sampling phase detector with linear output response is disclosed. The parallel sampling phase detector for use in data recovery. The device includes a voltage controlled oscillator (VCO) that generates ten separate phase signals using a five stage ring oscillator. Five linear phase detectors are employed in the device, each operating during one of five "window" intervals. The "window" intervals are non-overlapping, and are generated using preselected ones of the VCO output phases. The linear phase detectors each generate, respectively, a variable pulsewidth pump up signal wherein the pulsewidth of the pump up signal is proportional to a phase difference between the input data signal applied to the phase detector, and the output phase signals of the VCO. Each phase detector also generates a pump down signal that has a fixed pulsewidth. A loop filter determines the difference between the pump up and pump down signals and develops a control signal to vary the output frequency and phase of the VCO in accordance therewith. Each phase detector also operates as a deserializer, capturing, during the interval when the respective "window" signal is active, the data signal from the input data stream. The plurality of sampled data signals are captured by a data register, which then outputs an n-bit (5-bit) parallel format data word. The linear phase detector includes means for generating the pump down signal in response to the generation of the pump up signal.

128 citations

Patent
17 Mar 1998
TL;DR: In this paper, a mobile phone receiver comprises a first down converter using a first local oscillator frequency which can be tuned in frequency steps by a programmable digital frequency synthesizer PLL which is locked to a reference frequency.
Abstract: According to a second embodiment of the invention, a mobile phone receiver comprises a first down converter using a first local oscillator frequency which can be tuned in frequency steps by a programmable digital frequency synthesizer PLL which is locked to a reference frequency. The first down converter converts received signals to a first IF for filtering. A second down converter using a second local oscillator converts first IF signals to a second IF. The second local oscillator frequency is generated using a second digital frequency synthesizer PLL which locks the second oscillator to the reference frequency. A third down converter mixes the transmit frequency with the first local oscillator frequency to produce a lock frequency. A third digital frequency synthesizer PLL compares the lock frequency and the reference frequency to control generation of the transmit frequency.

127 citations

Patent
14 Nov 1988
TL;DR: In this paper, a sensorless control for DC permanent magnet brushless motor includes a feedback loop connected between the motor stator windings and the inverter which controls the timer at which current is provided to the various windings in sequence.
Abstract: A sensorless control for DC permanent magnet brushless motor includes a feedback loop connected between the motor stator windings and the inverter which controls the timer at which current is provided to the various windings in sequence. The control of the invention includes a voltage sensing network for sensing the back EMF on each motor winding when it is unenergized and comparing this voltage with a null point. For maximum torque this voltage has an optimum value and variation from this value produces an error signal which is integrated to produce a VCO drive signal. This signal controls the frequency of a VCO which in turn controls the switching times of the inverter.

127 citations

Journal ArticleDOI
TL;DR: This paper shows that fast rail-to-rail switching is required in order to achieve low phase noise and defines the effective Q factor for ring oscillators with large and nonlinear voltage swings and predicts its increase for CMOS processes with smaller feature sizes.
Abstract: This paper presents a framework for modeling the phase noise in complementary metal-oxide-semiconductor (CMOS) ring oscillators. The analysis considers both linear and nonlinear operations, and it includes both device noise and digital switching noise coupled through the power supply and substrate. In this paper, we show that fast rail-to-rail switching is required in order to achieve low phase noise. Further, flicker noise from the bias circuit can potentially dominate the phase noise at low offset frequencies. We define the effective Q factor for ring oscillators with large and nonlinear voltage swings and predict its increase for CMOS processes with smaller feature sizes. Our phase-noise analysis is validated via simulation and measurement results for ring oscillators fabricated in a number of CMOS processes.

126 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023168
2022344
2021269
2020388
2019469
2018530