Topic
Voltage-controlled oscillator
About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.
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15 Feb 1989
TL;DR: In this paper, a high-frequency integrated CMOS phase-locked loop (PLL) including two phase detectors is presented, which can lock on input frequencies in excess of 200 MHz with either or both detectors and consumes 500 mW from a single 5-V supply.
Abstract: A high-frequency integrated CMOS phase-locked loop (PLL) including two phase detectors is presented. The design integrates a voltage-controlled oscillator, a multiplying phase detector, a phase-frequency detector, and associated circuitry on a single die. The loop filter is external for flexibility and can be a simple passive circuit. A 2- mu m CMOS p-well process was used to fabricate the circuit. The loop can lock on input frequencies in excess of 200 MHz with either or both detectors and consumes 500 mW from a single 5-V supply. The oscillator is a ring of three inverting amplifiers and draws from an internal supply voltage regulated by an on-chip bandgap reference. This combination serves to reduce the supply and temperature sensitivity is less than 5%/V, and the oscillator temperature variation is 2.2% in the range of 25 to 80 degrees C. The typical oscillator tuning range is 112 to 209 MHz. The multiplying phase detector and phase-frequency detector exhibit input-referred phase offsets of >
117 citations
TL;DR: In this article, the authors present a rigorous phase noise analysis in the 1/f2 region for the differential CMOS LC-tank oscillator with both nMOS and pMOS switch pairs.
Abstract: This paper presents a rigorous phase noise analysis in the 1/f2 region for the differential CMOS LC-tank oscillator with both nMOS and pMOS switch pairs. A compact, closed-form phase noise equation is obtained, accounting for the noise contributions from both tank losses and transistors currents, which allows a robust comparison between LC oscillators built with either one or two switch pairs. The fabricated oscillator prototype is tunable between 2.15 and 2.35 GHz, and shows a phase noise of -144 dBc/Hz at 3 MHz offset from the 2.3 GHz carrier for a 4 mA bias current. The phase noise figure-of-merit is practically constant across the tuning range, with a minimum of 191.5 dBc/Hz. A reference single-switch-pair oscillator has been implemented and tested as well, and the difference between the phase noise levels displayed by the two oscillators is very nearly the one expected from theory
116 citations
TL;DR: In this article, the authors present a complete 2.5-V 77-GHz chipset for Doppler radar and imaging applications fabricated in SiGe HBT and SiGe BiCMOS technologies.
Abstract: This paper presents a complete 2.5-V 77-GHz chipset for Doppler radar and imaging applications fabricated in SiGe HBT and SiGe BiCMOS technologies. The chipset includes a 123-mW single-chip receiver with 24-dB gain and an IP1 dB of -21.7 dBm at 76-GHz local oscillator (LO) and 77-GHz RF, 4.8-dB double-sideband noise figure at 76-GHz LO and 1-GHz IF, and worst case -98.5 dBc/Hz phase noise at 1-MHz offset over the entire voltage-controlled oscillator tuning range at room temperature. Monolithic spiral inductors and transformers result in a receiver core area of 450 mum times 280 mum. For integration of an entire 77-GHz transceiver, a power amplifier with 19-dB gain, +14.5-dBm saturated output power, and 15.7% power-added efficiency is demonstrated. Frequency divider topologies for 2.5-V operation are investigated and measurement results show a 105-GHz static frequency divider consuming 75 mW, and a 107-GHz Miller divider consuming 33 mW. Measurements on all circuits confirm operation up to 100 deg C. Low-power low-noise design techniques for each circuit block are discussed.
116 citations
01 Jul 1999
TL;DR: This architecture is highly suitable for implementation with deep sub-/spl mu/m CMOS devices, which can attain improved switching speeds and reduce power dissipation during low voltage operation and a low voltage system-on-a-chip solution for multimedia applications.
Abstract: This brief proposes a new- architecture for the oversampling delta-sigma analog-to-digital converter (ADC) utilizing a voltage controlled oscillator (VCO). The VCO, associated with a pulse counter, works as a high-speed quantizer. This VCO quantizer also has the function of first-order noise shaping because the phase of the output pulse is an integrated quantity of the input voltage. If the maximum VCO frequency (fvm) is designed in the range of (2/sup bq/-2)fos
116 citations
14 Feb 2005
TL;DR: In this article, the authors developed a 27 and 40 GHz tuned amplifier and a 52.5 GHz voltage-controlled oscillator using 0.18mum CMOS for millimeter-wave design.
Abstract: We have developed a 27- and 40-GHz tuned amplifier and a 52.5-GHz voltage-controlled oscillator using 0.18-mum CMOS. The line-reflect-line calibrations with a microstrip-line structure, consisting of metal1 and metal6, was quite effective to extract the accurate S-parameters for the intrinsic transistor on an Si substrate and realized the precise design. Using this technique, we obtained a 17-dB gain and 14-dBm output power at 27 GHz for the tuned amplifier. We also obtained a 7-dB gain and a 10.4-dBm output power with a good input and output return loss at 40 GHz. Additionally, we obtained an oscillation frequency of 52.5 GHz with phase noise of -86 dBc/Hz at a 1-MHz offset. These results indicate that our proposed technique is suitable for CMOS millimeter-wave design
115 citations