Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.

System and method for voltage controlled oscillator automatic band selection

Abstract: A system and method for establishing the frequency of a voltage controlled oscillator ("VCO") within narrowly defined frequency bands. The resonant circuit of the VCO uses selectable elements, such as varactor diodes, to establish the operating frequency band. The control voltage of the VCO is varied within a voltage range to adjust the VCO output frequency. A phase detector compares the VCO output to a reference signal. If the phase detector determines that there is an imbalance between the VCO output and the reference signal, then it produces a signal which indicates whether the VCO frequency should be increased or decreased to match the reference signal frequency. If the control voltage is outside of the voltage range, then the system allows the operating frequency band to be changed by varying the number of selectable elements in response to the phase detector signal.

Progress and Challenges Towards Terahertz CMOS Integrated Circuits

Abstract: Key components of systems operating at high millimeter wave and sub-millimeter wave/terahertz frequencies, a 140-GHz fundamental mode voltage controlled oscillator (VCO) in 90-nm CMOS, a 410-GHz push-push VCO with an on-chip patch antenna in 45-nm CMOS, and a 125-GHz Schottky diode frequency doubler, a 50-GHz phase-locked loop with a frequency doubled output at 100 GHz, a 180-GHz Schottky diode detector and a 700-GHz plasma wave detector in 130-nm CMOS are demonstrated. Based on these, and the performance trends of nMOS transistors and Schottky diodes fabricated in CMOS, paths to terahertz CMOS circuits and systems including key challenges that must be addressed are suggested. The terahertz CMOS is a new opportunity for the silicon integrated circuits community.

A 19-mW 2.6-mm/sup 2/ L1/L2 dual-band CMOS GPS receiver

Abstract: This paper presents the design and implementation of an L1/L2 dual-band global positioning system (GPS) receiver. Dual-conversion with a low-IF architecture was used for dual-band operation. The receiver is composed of an RF preamplifier, down-conversion mixers, a variable-gain channel filter, a 2-bit analog-to-digital converter, and the full phase-locked-loop synthesizer including an on-chip voltage controlled oscillator. Fabricated in a 0.18-/spl mu/m CMOS technology, the receiver exhibits maximum gain of 95 dB and noise figures of 8.5 and 7.5 dB for L1 and L2, respectively. An on-chip variable-gain channel filter provides IF image rejection of 20 dB and gain control range over 60 dB. The receiver consumes 19 mW from a 1.8-V supply while occupying a 2.6-mm/sup 2/ die area including the ESD I/O pads.

A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop

Abstract: A 1.5-V 5.5-GHz fully integrated phase-locked loop (PLL) has been implemented in a 0.25-/spl mu/m foundry digital CMOS process. From a 5.5-GHz carrier, the in-band phase noise can be as low as -88 dBc/Hz at a 40-kHz offset, while the phase noise for the free-running VCO is -116 dBc/Hz at an 1-MHz offset. The VCO core current is 4.6 mA. The prescaler is implemented using a variation of the source-coupled logic (SCL) structure to reduce the switching noise, and thus to reduce the PLL side-band spurs. At -18 dBm signal power measured off chip, the switching noise coupled through substrate and metal interconnect generates spurs with power levels less than -99 dBm when the loop is open. A new charge-pump circuit is developed to reduce the current glitch at the output node. By incorporating a voltage doubler, the voltage dynamic range at the charge-pump output and thus the VCO control voltage range is increased from 1.3 to 2.6 V with immeasurable phase noise and spurious level degradation to the PLL. When the loop is closed, the power levels of side-band spurs at the offset frequency equal to the /spl sim/43-MHz reference frequency are < -69 dBc. The total power consumption of the PLL including that for the output buffers is /spl sim/23 mW.

Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

Abstract: This paper presents phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-sampling phase detector (SSPD) (which is also referred to as a sampling phase detector). The VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the sampling at the reference frequency. The underlying VCO sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 μm CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is <; -80 dBc. The PLL consumes 3.8 mW while the in-band phase noise is -121 dBc/Hz at 200 kHz and the output jitter integrated from 10 kHz to 100 MHz is 0.3psrms.