Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.

5-GHz SiGe HBT monolithic radio transceiver with tunable filtering

Abstract: A wide-band CDMA-compliant fully integrated 5-GHz radio transceiver was realized in SiGe heterojunction-bipolar-transistor technology with on-chip tunable voltage controlled oscillator (VCO) tracking filters. It allows for wide-band modulation schemes with bandwidth up to 20 MHz. The receiver has a single-ended single-sideband noise figure of 5.9 dB, more than 40 dB on-chip image rejection, an input compression point of -22 dBm, and larger than 70 dB local-oscillator-RF isolation. The phase noise of the on-chip VCO is -100 and -128 dBc/Hz at 100 kHz and 5 MHz offset from the carrier, respectively. The transmitter output compression point is +10 dBm. An image rejection better than 40 dB throughout the VCO tracking range has been demonstrated in the transmitter with all spurious signals 40 dB below the carrier. The differential transceiver draws 125 mA in transmit mode and 45 mA in receive mode from a 3.5-V supply.

A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration

Abstract: This paper presents a low-jitter, low-power and a small-area injection-locked all-digital PLL (IL-ADPLL). It consists of a dual-loop and a dual-VCO architecture in which one VCO (Replica) is placed in a TDC-less synthesizable ADFLL to provide continuous tracking of voltage and temperature variations. The other VCO (main) shares the control voltage with the replica VCO but is placed outside the loop and is injection-locked to lower its jitter and accurately set its frequency to the desired one. This approach avoids timing problems in the conventional ILPLL since the injection-locked VCO is placed outside the feedback loop. It also achieves a low power and a small area, due to the absence of a power hungry TDC and an area-consuming loop filter, while tracking any PVT variations. The IL-ADPLL is implemented in a 65 nm CMOS process and measurement results show that it achieves a 0.7ps RMS jitter at 1.2 GHz while having 1.6 mW and 0.97 mW power consumption with and without intermittent operation resulting in an FOM of -243 dB. It also consumes an area of only 0.022 mm2 resulting in the best performance-area trade-off system presented up-to-date.

Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers

Abstract: An LC-VCO based phase-locked loop (PLL) frequency synthesizer which incorporates loop bandwidth tracking is described. In order to minimize loop bandwidth variations resulting from changes in the LC-VCO gain, the proposed PLL employs an averaging varactor based split-tuned LC-VCO and a servo loop which sets the charge-pump current to be inversely proportional to the square of the oscillation frequency. The combination of these techniques maintains a constant loop bandwidth over a wide range of operating frequencies. Fabricated in a 0.13 mum CMOS technology, the prototype chip measures less than plusmn4% variation in KVCOmiddotICP / N (equivalent to the variation in PLL loop bandwidth) for an operating frequency range of 3.1 to 3.9 GHz.

Up/down conversion circuitry for radio transceiver

Abstract: A multi-channel RF receiver uses an image rejection mixer (e.g. double quadrature mixer) in the IF down conversion stage for image side band rejection (whereby use of an IF narrow band filter for image rejection may be omitted if desired) and comprises a simplified frequency synthesizer which generates both a “wandering” IF oscillator frequency and an RF oscillator frequency for the up/down conversion stages (being, for down conversion, from RF to IF and from IF to base band. The IF used for a particular RF carrier (channel) is selected so as to be both an integer (N) sub-harmonic of that RF carrier and within the operating frequency band of the image rejection mixer. Advantageously, the synthesizer comprises only one loop and one VCO, wherein the IF oscillator signal is produced from the RF oscillator signal by means of a frequency divider.

Phase controlled oscillator

Abstract: An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.