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Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.


Papers
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Patent
24 Jan 1992
TL;DR: In this paper, an improved ring oscillator is disclosed which can be formed in a semiconductor substrate, which includes inverters cascaded in a ring-like manner, and a diffused resistor R1 having a positive temperature coefficient and a polysilicon resistor R2 having a negative temperature coefficient for determining bias currents supplied to the inverters.
Abstract: An improved ring oscillator is disclosed which can be formed in a semiconductor substrate. The ring oscillator includes inverters cascaded in a ring-like manner, and a diffused resistor R1 having a positive temperature coefficient and a polysilicon resistor R2 having a negative temperature coefficient for determining bias currents supplied to the inverters. The oscillation frequency tends to decrease with a rise of ambient temperature based on a temperature characteristic of diffused resistor R1 and a temperature characteristic of the oscillator circuit itself; however, the change of oscillation frequency is compensated by a temperature characteristic of polysilicon resistor R2. Therefore, a reference clock signal generating circuit having an oscillation frequency which is not affected by change of the ambient temperature can be formed in the semiconductor substrate.

78 citations

Patent
01 Sep 1999
TL;DR: In this article, an improved spread spectrum clock generator circuit is provided which automatically compensates for variations in passive component values and system gain and charge pump current in a Phase Locked Loop circuit.
Abstract: An improved spread spectrum clock generator circuit is provided which automatically compensates for variations in passive component values and system gain and charge pump current in a Phase Locked Loop circuit. The pulse widths of the UP and DOWN outputs of the Phase Frequency Detector are monitored at particular intervals to determine the deviation error of these UP and DOWN signals, as compared to typical or nominal pulse-width durations. After an error is determined in the actual values of the pulse-width durations, the Phase Locked Loop (PLL) system is adjusted depending upon the magnitude and direction of the error signal. Changes in the PLL gain parameters, especially the VCO gain and charge pump current, have a significant effect on the PFD outputs, such that the width of the UP and DOWN signals vary as the frequency changes along the spread spectrum profile. At one portion of the spread spectrum profile, the “peak” (i.e., maximum) pulse width of these UP and DOWN signals will be a function of the spread spectrum's modulation profile and the PLL parameters. In addition to sampling for maximum pulse widths at the profile locations exhibiting peaks and valleys, the actual error profile may also exhibit a similarly large deviation from the target error profile at times just before the occurrence of the maximum peak and minimum peak (or “valley”). While determining precisely where within the profile these other substantial deviations occur is more difficult than monitoring the same signals at their maximum peaks, there are certain advantages to using the alternative locations along the error profile, which are described below.

78 citations

Journal ArticleDOI
TL;DR: A technique for reducing the supply voltage sensitivity of a ring oscillator using on-chip calibration is described, and a 1-V 0.13-mum CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 0.5 to 2 GHz.
Abstract: A technique for reducing the supply voltage sensitivity of a ring oscillator using on-chip calibration is described. A 1-V 0.13-mum CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 0.5 to 2 GHz. In the presence of a 10-mV 1-MHz VCO supply noise, the measured rms jitter of the proposed PLL with on-chip calibration is 3.95 ps at a 1.4-GHz operating frequency, while a conventional design measures 8.22 ps rms jitter. For 10-MHz VCO supply noise, the measured rms jitter is improved from 16.8 ps to 3.97 ps. The total power consumption of the PLL is 9.6 mW at 1.4 GHz, and the combined core die area of the PLL and the calibration circuitry is 0.064 mm2

78 citations

Journal ArticleDOI
24 Apr 2006
TL;DR: The RF transceiver is integrated with the baseband signal processing and associated passives in a 165-pad package, resulting in the first tri-band 3G radio transceiver with a digital interface which requires no external components.
Abstract: This paper describes the design and performance of the first tri-band (2100, 1900, 800/850 MHz) single-chip 3G cellular transceiver IC for worldwide use. The transceiver has been designed to meet all narrowband blocker, newly proposed Adjacent Channel II, and Category 10 HSDPA (High Speed Downlink Packet Access) requirements. The design is part of a reconfigurable reference platform for multi-band, multi-mode (GSM/EDGE + WCDMA) radios. The zero-IF receiver is comprised of a novel multi-band quadrature mixer, seventh-order baseband filtering, and a novel DC offset correction scheme, which exhibits no settling time or peak switching transients after gain steps. The receiver lineup is designed to optimize HSDPA throughput and minimize sensitivity to analog baseband filter bandwidth variations. The direct-launch transmitter is made up of a third-order baseband filter, an I/Q modulator with variable gain, an integrated transformer, an RF variable gain amplifier, and a power amplifier driver. At +9.5-dBm output power, the transmitter achieves an error vector magnitude (EVM) of 4%. Fractional-N synthesizers achieve fast lock times of 50 /spl mu/s (150 /spl mu/s) within 20 ppm (0.1 ppm). Automatically calibrated, integrated VCOs achieve a 1.6-GHz tuning range to facilitate coverage over all six 3GPP frequency bands. The IC draws 34 mA in receive (18-mA receiver plus 16-mA fractional-N PLL/VCO) and 50 to 62 mA in transmit (-76 dBm to +9.5 dBm), including PLL/VCO, using a 2.775-V supply voltage. The RF transceiver is integrated with the baseband signal processing and associated passives in a 165-pad package, resulting in the first tri-band 3G radio transceiver with a digital interface which requires no external components.

78 citations

Journal ArticleDOI
TL;DR: A 1-9 GHz linear-wide-tuning-range quadrature ring oscillator has been designed and fabricated in UMC 0.13?m CMOS process.
Abstract: A 1-9 GHz linear-wide-tuning-range quadrature ring oscillator has been designed and fabricated in UMC 0.13 ?m CMOS process. The chip was wire-bonded on printed circuit board and tested, showing a liner tuning range from 1 GHz to 9 GHz. Comparative study with other differential ring oscillators demonstrates the advantages of this design in low power consumption and linear-tuning. The oscillator was designed as the voltage controlled oscillator (VCO) for a non-contact vital sign radar sensor. It can also be used for other applications such as ultra-wideband (UWB) impulse radio and clock recovery in broadband optical communications.

78 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023168
2022344
2021269
2020388
2019469
2018530