Voltage-controlled oscillator

About: Voltage-controlled oscillator is a research topic. Over the lifetime, 23896 publications have been published within this topic receiving 231875 citations. The topic is also known as: VCO.

A 1.8 GHz highly-tunable low-phase-noise CMOS VCO

Abstract: A 1.8 GHz fully integrated Voltage Controlled Oscillator (VCO) is presented. Through inductor optimization, the phase noise is as low as -127.5 dBc/Hz at 600 kHz and -142.5 dBc/Hz at 3 MHz. A 28% wide tuning range is achieved with a 1.8 V power supply. The VCO exceeds the DCS-1800 phase noise requirements with at least 4 dB over the whole DCS-1800 frequency band. The VCO is implemented in a 2-metal layer, 0.25 /spl mu/m standard CMOS technology, using no external components nor additional processing steps.

QPSK and 16 QAM self-generating synchronous direct downconversion demodulator

Abstract: A system for recovering and demodulating a carrier includes a carrier recovery loop and a data detector. The carrier recovery loop receives the carrier as an input and produces a recovered carrier at a frequency approximately equal to that of the carrier. The carrier recovery loop includes a downconverting mixer, a ×5 multiplier, a ×4 multiplier, and a phase locked loop. The downconverting mixer receives the carrier input, and the phase locked loop provides a VCO reference frequency through the ×5 multiplier to the downconverting mixer, which provides a frequency shifted signal. The frequency shifted signal is passed through the ×4 multiplier as input to the phase locked loop. The data detector receives the carrier and the recovered carrier as inputs and uses the recovered carrier to demodulate the carrier and detect I channel data and Q channel data.

A 3 V 4 GHz nMOS voltage-controlled oscillator with integrated resonator

Abstract: There is increasing interest in implementing the key components of radio transceivers in mature silicon technologies. Submicron CMOS technology combined with low-parasitic on-chip passives is emerging as a strong candidate to implement many of these components that traditionally have been realized using GaAs. Fully-monolithic voltage-controlled oscillators (VCOs) present many challenges to any technology since they require low-parasitic high-quality passives for acceptable tuning range and phase noise levels, and low-power active devices at microwave frequencies. A 1.8 GHz CMOS VCO with a 4.5% tuning range is not fully monolithic, as it requires bonding wires as inductive elements in the tank circuit. Fully-integrated LC resonators offer the advantages of low cost and reduced sensitivity to packaging parasitics at the price of lower resonator Q values due to the losses in on-chip spiral inductors and varactor diodes. The authors present a fully-monolithic VCO based on an nMOS gain stage and an integrated tunable resonator operating at 4 GHz with a 9% tuning range. The technology is a 5-level metal 0.5 /spl mu/m BiCMOS process (BiCMOS4S+). No bipolar devices are used in the active circuitry.

A 16–18.8-GHz Sub-Integer-N Frequency Synthesizer for 60-GHz Transceivers

Abstract: An 18-GHz range frequency synthesizer is implemented in 0.13-mum SiGe BiCMOS technology as part of a 60-GHz superheterodyne transceiver chipset. It provides for RF channels of 56.5-64 GHz in 500-MHz steps, and features a phase-rotating multi-modulus divider capable of sub-integer division. Output frequency range from the synthesizer is 16.0 to 18.8 GHz, while the enabled RF frequency range is 3.5 times this, or 55.8 to 65.8 GHz. The measured RMS phase noise of the synthesizer is 0.8deg (1 MHz to 1 GHz integration), while phase noise at 100-kHz and 10-MHz offsets are -90 and -124 dBc/Hz, respectively. Reference spurs are 69 dBc; sub-integer spurs are -65 dBc; and combined power consumption from 1.2 and 2.7 V is 144 mW.

A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN

Abstract: This paper introduces a fully integrated 2x2 two-stream MIMO radio SoC that integrates all of the functions of an 802.11n WLAN. The 0.13 mum CMOS radio SoC, which integrates two dual-band (2.4 GHz and 5 GHz) RF transceivers, analog baseband filters, data converters, digital physical layer, media access controller, and a PCI Express interface, provides a low-cost low-power small-form-factor WLAN solution. The MIMO radio comprises two identical dual-band transceivers that share a common frequency synthesizer capable of operating in both integer-N and fractional-N modes. In 2.4 GHz mode, the transceiver uses a direct-conversion architecture with a 3.2 GHz fractional-N frequency synthesizer. Direct conversion is used primarily because of its simplicity and the area reduction it offers by eliminating the need for an IF path. A 3.2 GHz synthesizer frequency is used to avoid VCO pulling. The 3.2 GHz synthesizer output fvco is divided by two and then mixed with the original 3.2 GHz fvco to generate a 4.8 GHz frequency. This 4.8 GHz signal at twice the RF frequency is distributed to both transceivers. Within each transceiver, the 4.8 GHz signal is divided by two to generate the 2.4 GHz in-phase and quadrature LO signals. In the 5 GHz mode, the transceiver uses a sliding-IF dual-conversion architecture, in which the RF and IF LO signals are centered at 2/3 fRF and 1/3 fRF, respectively. The frequency synthesizer, operating in integer-N mode, thus provides a 3.2 GHz RF LO signal that is buffered and distributed to both transceivers. Within each transceiver a resistively loaded divide-by-two circuit is used to generate the quadrature LO signals at 1/3 fRF. The channel center frequencies in the 5 GHz band allow integer-N operation of the synthesizer with a relatively high reference frequency, thus improving the phase noise.