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Voltage multiplier

About: Voltage multiplier is a research topic. Over the lifetime, 3889 publications have been published within this topic receiving 50497 citations. The topic is also known as: voltage doubler.


Papers
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Journal ArticleDOI
TL;DR: An improved voltage multiplier technique has been developed for generating +40 V internally in p-channel MNOS integrated circuits to enable them to be operated from standard +5- and -12-V supply rails.
Abstract: An improved voltage multiplier technique has been developed for generating +40 V internally in p-channel MNOS integrated circuits to enable them to be operated from standard +5- and -12-V supply rails. With this technique, the multiplication efficiency and current driving capability are both independent of the number of multiplier stages. A mathematical model and simple equivalent circuit have been developed for the multiplier and the predicted performance agrees well with measured results. A multiplier has already been incorporated into a TTL compatible nonvolatile quad-latch, in which it occupies a chip area of 600 /spl mu/m/spl times/240 /spl mu/m. It is operated with a clock frequency of 1 MHz and can supply a maximum load current of about 10 /spl mu/A. The output impedance is 3.2 M/spl Omega/.

1,726 citations

Journal ArticleDOI
TL;DR: In this paper, the authors comprehensively review and classify various step-up dc-dc converters based on their characteristics and voltage-boosting techniques, and discuss the advantages and disadvantages of these voltage boosting techniques and associated converters.
Abstract: DC–DC converters with voltage boost capability are widely used in a large number of power conversion applications, from fraction-of-volt to tens of thousands of volts at power levels from milliwatts to megawatts. The literature has reported on various voltage-boosting techniques, in which fundamental energy storing elements (inductors and capacitors) and/or transformers in conjunction with switch(es) and diode(s) are utilized in the circuit. These techniques include switched capacitor (charge pump), voltage multiplier, switched inductor/voltage lift, magnetic coupling, and multistage/-level, and each has its own merits and demerits depending on application, in terms of cost, complexity, power density, reliability, and efficiency. To meet the growing demand for such applications, new power converter topologies that use the above voltage-boosting techniques, as well as some active and passive components, are continuously being proposed. The permutations and combinations of the various voltage-boosting techniques with additional components in a circuit allow for numerous new topologies and configurations, which are often confusing and difficult to follow. Therefore, to present a clear picture on the general law and framework of the development of next-generation step-up dc–dc converters, this paper aims to comprehensively review and classify various step-up dc–dc converters based on their characteristics and voltage-boosting techniques. In addition, the advantages and disadvantages of these voltage-boosting techniques and associated converters are discussed in detail. Finally, broad applications of dc–dc converters are presented and summarized with comparative study of different voltage-boosting techniques.

1,230 citations

Journal ArticleDOI
TL;DR: A novel fully integrated passive transponder IC with 4.5- or 9.25-m reading distance at 500-mW ERP or 4-W EIRP base-station transmit power, operating in the 868/915-MHz ISM band with an antenna gain less than -0.5 dB.
Abstract: This paper presents a novel fully integrated passive transponder IC with 4.5- or 9.25-m reading distance at 500-mW ERP or 4-W EIRP base-station transmit power, respectively, operating in the 868/915-MHz ISM band with an antenna gain less than -0.5 dB. Apart from the printed antenna, there are no external components. The IC is implemented in a 0.5-/spl mu/m digital two-poly two-metal digital CMOS technology with EEPROM and Schottky diodes. The IC's power supply is taken from the energy of the received RF electromagnetic field with help of a Schottky diode voltage multiplier. The IC includes dc power supply generation, phase shift keying backscatter modulator, pulse width modulation demodulator, EEPROM, and logic circuitry including some finite state machines handling the protocol used for wireless write and read access to the IC's EEPROM and for the anticollision procedure. The IC outperforms other reported radio-frequency identification ICs by a factor of three in terms of required receive power level for a given base-station transmit power and tag antenna gain.

875 citations

Journal ArticleDOI
TL;DR: In this article, the use of the voltage multiplier technique applied to the classical non-isolated dc-dc converters in order to obtain high step-up static gain, reduction of the maximum switch voltage, zero current switching turn-on was introduced.
Abstract: This paper introduces the use of the voltage multiplier technique applied to the classical non-isolated dc-dc converters in order to obtain high step-up static gain, reduction of the maximum switch voltage, zero current switching turn-on. The diodes reverse recovery current problem is minimized and the voltage multiplier also operates as a regenerative clamping circuit, reducing the problems with layout and the EMI generation. These characteristics allows the operation with high static again and high efficiency, making possible to design a compact circuit for applications where the isolation is not required. The operation principle, the design procedure and practical results obtained from the implemented prototypes are presented for the single-phase and multiphase dc-dc converters. A boost converter was tested with the single-phase technique, for an application requiring an output power of 100 W, operating with 12 V input voltage and 100 V output voltage, obtaining efficiency equal to 93%. The multiphase technique was tested with a boost interleaved converter operating with an output power equal to 400 W, 24 V input voltage and 400 V output voltage, obtaining efficiency equal to 95%.

702 citations

Journal ArticleDOI
TL;DR: A new design for an energy harvesting device is proposed in this paper, which enables scavenging energy from radiofrequency (RF) electromagnetic waves by proposing a dual-stage energy harvesting circuit composed of a seven-stage and ten-stage design, the former being more receptive in the low input power regions, while the latter is more suitable for higher power range.
Abstract: A new design for an energy harvesting device is proposed in this paper, which enables scavenging energy from radiofrequency (RF) electromagnetic waves. Compared to common alternative energy sources like solar and wind, RF harvesting has the least energy density. The existing state-of-the-art solutions are effective only over narrow frequency ranges, are limited in efficiency response, and require higher levels of input power. This paper has a twofold contribution. First, we propose a dual-stage energy harvesting circuit composed of a seven-stage and ten-stage design, the former being more receptive in the low input power regions, while the latter is more suitable for higher power range. Each stage here is a modified voltage multiplier, arranged in series and our design provides guidelines on component choice and precise selection of the crossover operational point for these two stages between the high (20 dBm) and low power (-20 dBm) extremities. Second, we fabricate our design on a printed circuit board to demonstrate how such a circuit can run a commercial Mica2 sensor mote, with accompanying simulations on both ideal and non-ideal conditions for identifying the upper bound on achievable efficiency. With a simple yet optimal dual-stage design, experiments and characterization plots reveal approximately 100% improvement over other existing designs in the power range of -20 to 7 dBm.

444 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202370
2022151
2021106
2020148
2019161
2018117