Showing papers on "Voltage regulator published in 1997"

A new mathematical model and control of a three-phase AC-DC voltage source converter

Abstract: A new mathematical model of the power circuit of a three-phase voltage source converter (VSC) was developed in the stationary and synchronous reference frames. The mathematical model was then used to analyze and synthesize the voltage and current control loops for the VSC. Analytical expressions were derived for calculating the gains and time constants of the current and voltage regulators. The mathematical model was used to control a 140-kW regenerative VSC. The synchronous reference-frame model was used to define feedforward signals in the current regulators to eliminate the cross coupling between the d and q phases. It allowed the reduction of the current control loops to first-order plants and improved their tracking capability. The bandwidths of the current and voltage-control loops were found to be approximately 20 and 60 times (respectively) smaller than the sampling frequency. All control algorithms were implemented in a digital signal processor. All results of the analysis were experimentally verified.

Fuzzy dynamic programming approach to reactive power/voltage control in a distribution substation

Abstract: A fuzzy dynamic programming (FDP) approach is proposed for solving the reactive power/voltage control problem in a distribution substation. The main purpose is to improve the voltage profile on the secondary bus and restrain the reactive power flow into a main transformer at the same time. To reach our objectives, the load tap changer (LTC) usually installed in a main transformer is employed to adjust the secondary voltage and the capacitor connected to the secondary bus is employed to compensate the reactive power flow for the load demands. We first forecast the real and reactive power demands of a main transformer and its primary voltages for the next day. With these forecasting data at hand, a fast LTC tap position estimation formula that takes the load models into account is derived to effectively reduce the computational burden for the proposed approach. Practical constraints on bus voltage limits, maximum allowable number switching operations in a day for the LTC and capacitor and the tolerable worst power factor for a main transformer are also considered. To demonstrate the usefulness of the proposed approach, reactive power/voltage control at a distribution substation within the service area of Taipei City District Office of Taiwan Power Company is investigated. It is found that a proper dispatching schedule for the LTC and capacitor can be reached by the proposed approach.

One pin error amplifier and switched soft-start for an eight pin PFC-PWM combination integrated circuit converter controller

Abstract: A combination PFC-PWM integrated circuit converter controller having a power factor correction stage and a pulse-width modulation stage. The power factor correction stage provides unity power factor and a regulated intermediate output voltage by sensing a current in the power factor correction circuit and by sensing the regulated intermediate output voltage in a voltage control loop. The regulated intermediate output voltage is sensed by an error amplifier that includes a current mirror. A dc supply voltage for powering the integrated circuit is generated that is representative of the regulated intermediate output voltage. The dc supply voltage is sensed for an overvoltage protection function. By sensing the intermediate regulated output voltage in the voltage control loop and by sensing the dc supply voltage for overvoltage protection, a component failure is less likely to affect both functions than if a single voltage was sensed for both functions. The pulse-width modulation stage waits a predetermined delay time after start up for the output voltage to rise before beginning the pulse-width modulation function. The delay time is determined by an amount of time taken to charge a capacitor to a predetermined voltage after start up. The capacitor is charged by a current source that is switched on and off according to a clock signal such that the capacitor is charged only a portion of time. Therefore, a larger current source may be used than otherwise which results in more reliable control of the delay time.

A high-efficiency variable-voltage CMOS dynamic dc-dc switching regulator

Abstract: Dynamically adjusting supply voltage based on processing load in applications that involve variable workloads to reduce energy consumption has been proposed. A similar idea for tracking temperature and process variations using a dynamic switching regulator has also been proposed. In this paper a buck-converter switching regulator chip for use in an energy-on-demand system is shown.

Low-dropout voltage regulator incorporating a current efficient transient response boost circuit

Abstract: An improved low-dropout ("LDO") voltage regulator incorporates a transient response boost circuit which is added to the slew-rate limited node at the control terminal of the LDO voltage regulator output transistor and provides improved transient response performance to the application of various load current step stimuli while requiring no standby or quiescent current during zero output current load conditions. The transient boost circuit supplies current to the slew-rate limited node only upon demand and may be constructed as either a localized positive feedback loop or a number of switching devices which conduct current only during slew-rate conditions.

Standby power system

Abstract: The standby power system (20) provides backup power to a load, such as a computer system, when main AC line power fails. A system DC battery (30) voltage is converted to an AC output voltage signal at line voltage levels by a power conversion system including a high frequency push-pull inverter (56), a light-weight low-cost high frequency transformer (52), a rectifier (54), and a line frequency inverter (56). The high frequency inverter (56) is controlled to provide high frequency battery voltage pulse bursts separated by low frequency zero voltage dead times which are boosted by the transformer (52) to line voltage levels and rectified by the rectifier (54). The line frequency inverter (56) is controlled to provide the rectified line voltage level pulse bursts to the standby power system (20) output in the form of a stepped square wave output signal at line frequencies. The system controller (38) detects the occurrence of AC line faults using a single digital line sense signal. Since analog-to-digital conversion of the power system input and output voltage waveforms is not required for line fault detection (44) or output voltage control, the system controller (38) may be implemented using a low-cost microprocessor (38).

Active common mode canceler

Abstract: An active common mode canceler includes a voltage detection circuit including a plurality of capacitors connected to the output terminals of a power converter for performing power conversion by switching a power semiconductor device and serving to detect a common mode voltage generated when the power semiconductor device is switched, a push-pull type emitter follower circuit which is controlled by the common mode voltage detected by the voltage detection voltage to output a voltage equal in magnitude and opposite in polarity to the common mode voltage, and a common mode transformer having multiple windings and serving to cancel out the common mode voltage by superimposing the voltage output from the emitter follower circuit on the output from the power converter.

Dynamic series voltage restoration for sensitive loads in unbalanced power systems

Abstract: A method and apparatus is provided for restoring a sagging voltage signal on a power transmission line, caused by a remote fault in the utility power system, to a balanced three-phase condition at the pre-fault voltage level. Voltage restoration is provided by injecting a voltage signal in series with the power transmission line which restores the load voltage vectors to the pre-fault condition. The restored load voltage vectors are rotated by a selected phase angle such that zero real power flow is associated with the voltage restoration. The voltage compensation signal may be injected into the power transmission line by connecting a voltage compensator inverter in series with the transmission line. The voltage compensator inverter may be controlled to provide the desired injected voltage signal using a synchronous reference frame based controller. The voltage restoration function may be achieved by controlling the inverter to generate an inverter voltage signal which restores the positive sequence load voltage component to pre-fault conditions, and which cancels negative and zero sequence components of the load voltage signal. Phase rotation to ensure the zero power flow condition is achieved by controlling the inverter to generate an inverter voltage signal which balances the voltage across a DC bus capacitor which powers the inverter. Uninterruptible power supply and active harmonic filtering functions may be provided by the system.

Semiconductor integrated circuit including voltage converter effective at low operational voltages

Abstract: A push-pull type output circuit is used in the differential amplifier of a voltage converter circuit. The threshold voltage of the driving transistor is set lower than the voltages of the transistors of the other circuits to operate the differential amplifier at a voltage higher than the power supply voltage. By using the push-pull type output circuit, the amplitude increases and it is possible to raise the capacity of the driving transistor. Moreover, by setting the threshold voltage of the driving transistor of the buffering circuit lower than the threshold voltages of the transistors of the other circuits, it is possible to further raise the driving capacity. Increase of the sub-threshold current due to lowering of the threshold voltage can be prevented by operating the differential amplifier at a voltage higher than the power supply voltage.

Dual adjustable voltage regulators

Abstract: A dual adjustable voltage regulator combining a DC--DC switching regulator with a linear regulator implemented on a single chip is disclosed. The invention provides switching circuitry that can select between a fixed output voltage level and a user-adjustable output voltage. The circuit further provides means to automatically detect and generate power supply voltage levels as required by the system.

Method and apparatus for isolated flyback regulator control and load compensation

Abstract: Control circuits for a flyback switching voltage regulator that uses magnetic flux sensing are provided. These circuits include a flyback error amplifier circuit, a logic circuit, and a load compensation circuit. The flyback error amplifier circuit allows a flyback voltage pulse from a primary transformer winding to be employed for output voltage regulation. The logic circuit provides appropriate timing and control signals for the flyback error amplifier circuit. The load compensation circuit compensates for parasitic impedance contributions to the flyback voltage pulse without altering the stability of the flyback regulator.

Ripple cancellation circuit with fast load response for switch mode voltage regulators with synchronous rectification

Abstract: A switch mode voltage regulator with synchronous rectification that produces ripple cancellation with fast load response is described. The switch mode voltage regulator comprises a main step-down regulator with synchronous rectification with an auxiliary step-down regulator that produces an output ripple cancellation current that is equal but opposite to the output ripple of the main regulator during static load conditions. During changing load conditions a feedback control circuit changes the duty cycle of the main regulator while a time-delay circuit prevents a change of the duty cycle in the auxiliary regulator. Thus, the main regulator is allowed to change its average current while preventing a counteracting average current change in the auxiliary regulator. An embodiment is described in which the duty cycle in the auxiliary regulator is changed in phase with the duty cycle of main regulator to further improve the dynamic response to load changes. A sub-cycle circuit is also described that overrides the feedback control circuit to improve the dynamic response to load changes. Accordingly, a fast transient response can be achieved with a switch mode regulator that has a low ripple voltage.

An experimental confirmation of automatic threshold voltage convergence in a flash memory using alternating word-line voltage pulses

Abstract: A flash memory using the alternating word-line voltage pulses is experimentally studied. Relations between pulse count and the threshold voltages of the cell are obtained. An automatic threshold voltage convergence was confirmed by the relation, and the threshold voltage is successfully controlled by the word-line pulse voltage. An application to a multi-level flash memory is proposed.

Device for supplying voltage in a motor vehicle including two batteries and having improved reliability

Abstract: A device for supplying voltage in a motor vehicle is described in which there is at least one generator that can furnish an generator-speed-dependent output voltage without voltage regulation. The at least one generator is preferably a three-phase alternator with a plurality of stator windings whose electrical connections are switchable at predetermined generator speeds by a control unit to provide the generator-speed dependent output voltage. In a following power control unit, this generator speed-dependent voltage is rectified by means of at least one controlled rectifier bridge and via assigned voltage converters is converted into a plurality of directly voltages of different magnitude. These direct voltages are supplied to the individual on-board electrical system components via electronic vehicle body power control system units. By optimal-efficiency triggering of the controlled rectifier bridges and additional safety and/or emergency provisions, the functional capability and power capability of the voltage supply unit are assured.

Regulator circuit and semiconductor integrated circuit device having the same

Abstract: A regulator circuit includes an output circuit outputting an output voltage based on a control voltage, a reference voltage generating circuit generating a reference voltage, an output voltage control circuit comparing the reference voltage with a voltage depending on the output voltage and producing the control voltage based on a comparison result, and a power supply circuit which supplies the reference voltage generating circuit and the output voltage control circuit with a first power supply voltage which is different from a second power supply voltage supplied to the output circuit.

Circuitry for a low internal voltage integrated circuit

Abstract: A technique and circuitry for interfacing an integrated circuit manufactured using technology compatible with one voltage level to other integrated circuits compatible with a different voltage level. In particular, the integrated circuit is fabricated using technology compatible with an internal supply voltage level. Externally, the integrated circuit will interface with an external supply voltage level, above the internal supply voltage. The input and output signals to and from the integrated circuit will be compatible with the external supply level. The integrated circuit may include a voltage down converter (1330) and level shifter (1317).

Two-phase bootstrapped CMOS switch drive technique and circuit

Abstract: A circuit that produces a gate drive voltage for a MOS transistor switch, that receives an input voltage "on" a source terminal, includes a first input that receives the input voltage, a second input that receives a bias voltage, and a voltage storage element. A first switch connects the voltage storage element to sample one of the input voltage and the bias voltage during a first of first and second non-overlapping time intervals. A second switch connects the voltage storage element to increase the sampled voltage by another of the input voltage and the bias voltage to the gate drive voltage during the second non-overlapping time interval, while maintaining the gate drive voltage less than a breakdown voltage of the MOS transistor switch. A third switch connects the voltage storage element to provide the gate drive voltage to the MOS transistor switch such that a gate-to-source voltage of the MOS transistor switch is maintained approximately constant.

MOS charge pump generation and regulation method and apparatus

Abstract: MOS charge pump generation and regulation method and apparatus of the general type used in a non-volatile memory chip for generating high voltages (˜20 v). This invention utilizes a current controlled oscillator to generate the clock for the charge pump voltage multiplier. The oscillator frequency is designed to compensate for process, temperature and power supply variations. The charge pump shunt regulator only utilizes regular low voltage NMOS and PMOS from a standard CMOS process. A reference voltage scheme is used in which a regular low voltage PMOS is used as a mirror diode (reference PMOS) to precisely realize a control voltage for the shunting NMOS without violating any breakdown mechanism, i.e. PMOS gated diode breakdown and P+ to n-well junction breakdown. A medium voltage level is also used to buffer the shunting NMOS transistors from gated diode breakdown. A native NMOS cascode current mirror is used to precisely mirror the current to achieve minimum headroom voltage with minimum circuit area.

Non-volatile static random access memory and methods for using same

Abstract: The state of a memory cell is stored by selectively imbalancing threshold voltages of storage elements of the memory cell. The threshold voltages may be selectively imbalanced by pulsing the supply voltage for the memory cell from an operating voltage level to a programming voltage level. This may be accomplished by raising the supply voltage from the operating voltage level to the programming voltage level for a period of time sufficient to store the state of the memory cell by monitoring the leakage current from the programming voltage level such that it just falls below a preestablished limit. Alternatively, the supply voltage may be repeatedly toggled between the operating voltage level and the programming voltage level for fixed time intervals until the state of the memory cell is stored. The number of toggling operations may be determined by monitoring the leakage current such that it just falls exceeds a predetermined limit. The programming voltage level may be approximately twice the operating voltage level or greater. Selectively imbalancing the threshold voltages of the storage elements may be accomplished by creating a first electric field within a first of the storage elements to tunnel electrons off of a floating gate of the first storage element and creating a second electric field within a second of the storage elements to inject the electrons onto a floating gate of the second storage element. Preferably, these electric fields are created simultaneously by applying the programming voltage to the memory cell.

Minimizing harmonic voltage distortion with multiple current-constrained active power line conditioners

Abstract: The purpose of this paper is to present a useful algorithm for minimizing harmonic voltage distortion levels with multiple current-constrained active power line conditioners (APLCs) in a power system. The algorithm contains a sensitivity analysis-based single-APLC placement procedure, and uses a nonlinear programming optimizer GRG2 to improve the solution if necessary. The usefulness of this algorithm is then illustrated by a distribution system example. Simulation results show that the algorithm is simple, computationally efficient and can be easily extended to minimize several other alternative harmonic-related network objective functions.

DC-to-DC converter having charge pump and associated methods

Abstract: A DC-to-DC converter includes a charge pump, connected to a switch drive and to an input voltage, for selectively boosting the supply voltage to the switch drive; and a charge pump controller cooperating with the charge pump for controlling the supply voltage to the switch drive. The charge pump preferably includes a plurality of transistors connected in series with the supply voltage, and at least one capacitor connected to the transistors. The charge pump controller passes through the input voltage to the supply voltage based upon the input voltage being above a first voltage; boosts the supply voltage to a substantially constant value based upon the input voltage being less than the first voltage and greater than or equal to a second voltage wherein the second voltage is less than the first voltage; and boosts the supply voltage by a multiple of the input voltage based upon the input voltage being less than the second voltage. Method aspects of the invention are also disclosed.

Load pole stabilized voltage regulator circuit

Abstract: A voltage regulator with load pole stabilization is disclosed. An error amplifier has a non-inverting input receiving a reference voltage and an inverting input receiving a feedback voltage from the output of the voltage regulator. A gain stage has an input connected to the output of the error amplifier and an output connected to a pass transistor that provides current to a load. A variable impedance device such as a FET transistor configured as a variable resistor is connected between the input and output of the gain stage to provide variable zero to cancel the varying pole when the output current drawn by the load fluctuates. Consequently, the disclosed voltage regulator has high stability without a significant increase in power dissipation.

Dual-output dc-dc power supply

Abstract: A multi-output power supply having half-brick dimensions includes a forward converter circuit which receives a DC input voltage and in response to a first control signal generates a first DC output voltage at a first level; and a buck regulator circuit which receives the first DC output voltage from the forward converter circuit. In response to a second control signal, the buck regulator generates a second DC output voltage at a second level.

Low drop-out voltage regulator with PMOS pass element

Abstract: A voltage regulator circuit includes: a first MOS transistor 12 coupled between a voltage supply line and an output node 44, the first MOS transistor 12 providing a stable voltage on the output node 44; a source follower 24 coupled to a gate of the first MOS transistor 12; an amplifier 38 coupled to a gate of the source follower 24 for controlling the response of the first MOS transistor 12; negative feedback circuitry coupled between the output node 44 and the amplifier 38, the feedback circuitry providing feedback to the amplifier 38; a current conveyer 46 coupled to the first MOS transistor 12; and positive feedback circuitry 26 coupled between the current conveyer 46 and the source follower 24.

Optimal soft starting of voltage-controller-fed IM drive based on voltage across thyristor

Abstract: AC voltage controllers are used as induction motor starters in fan or pump drives and the crane hoist drives. This paper presents a method of identifying the end of soft start of an AC voltage controller-fed induction motor (IM) drive based on the voltage across the nonconducting thyristor through a dynamic simulation of the whole drive system. A two point current minimization technique is adopted to operate the drive system at the required optimal voltage under all operating conditions. This minimizes the motor losses. Graphic modeling of the whole drive system is done in a modular format using Design Star and dynamic simulation is done using SABER. The dynamic simulation results of the whole drive system are supported with experimental data.

Dual-loop spread-spectrum clock generator with master PLL and slave voltage-modulation-locked loop

Abstract: A clock generator produces a frequency-modulated clock. A master phase-locked loop (PLL) includes a voltage summer that outputs a voltage to a voltage-controlled oscillator (VCO). The voltage to the VCO determines the frequency of the clock generated. A modulated voltage is subtracted by the voltage summer to produce voltage and thus frequency modulations. This modulated voltage is produced by a second loop that operates as a slave to the master PLL. The slave loop is a voltage-locked loop. The peak amplitude of the modulated voltage is locked to a control voltage of the master PLL. The control voltage is a stable voltage input to the voltage summer that is generated by phase comparisons of the output clock to a reference clock. To overcome the problem of locking to the modulating output clock, phase comparison is performed only at the same point in the modulation cycle, at the beginning of each modulation cycle. Thus modulations do not affect phase comparisons. The modulated voltage is generated by a waveform generator in the slave loop. The waveform generator is controlled by a feedback divider that also controls when phase comparison is performed. The amplitude of the waveform is adjusted to track the control voltage of the master PLL by comparing the control voltage to the modulated voltage, but only at the beginning of the modulation cycle. The modulation amplitude is kept constant over different supply voltages, ambient temperatures, and process corners.

Field-oriented control of an induction machine in the field-weakening region with DC-link and load disturbance rejection

Abstract: A method of actively maintaining voltage margin in field-oriented induction machine controllers is proposed. A voltage-margin controller is developed that rejects DC-link and load disturbances, such that current regulation and field orientation is maintained. In addition, the voltage-margin controller coupled with rotor-flux-oriented control is shown to provide maximum torque capability equivalent to stator-flux-oriented control.

Low consumption linear voltage regulator with high supply line rejection

Abstract: A linear type of voltage regulator, having an input terminal adapted to receive a supply voltage thereon, and an output terminal adapted to deliver a regulated output voltage, includes a power transistor and a driving circuit therefor. The driving circuit includes an operational amplifier having a differential input stage biased by a bias current which varies proportionally with the output current of the regulator.

Distributed voltage converter apparatus and method for high power microprocessor with array connections

Abstract: The present invention provides a relief to the low voltage, high current spiral trend being seen in the microprocessor industry. A microprocessor module is designed to receive a voltage V2, which is substantially higher than a logic gate utilization voltage V3. V2 is supplied at a current rating of I2 to a plurality of within-module voltage converters, designated as 220a, 220n, which directly distribute voltage V3 and the appropriate current portion I3 to the respective logic gates 210. Preferably, voltage V2 is substantially greater in magnitude than voltage V3, typically V2:V3 being at least 5:1 but preferably 40:1 to as much as 100:1. By example, V2=50 vdc, 12=3 amps and V3=1.0 vdc would satisfy the ratio considerations. The microprocessor loads serviced by the present invention constitute millions of logic gates requiring low voltages ranging from 0.75 Vdc to 1.5 Vdc. Other microprocessor loads, such as cache, can be powered with flip chip technology using the technique of the present invention. A selected number of microprocessor logic gates, designated as numeral 210, are powered through electrical interconnections 205 (bumps), from respective voltage converters 220a . . . 220n. Each voltage converter includes power conversion components, namely a pre-regulator pulse width modulator controller circuit 223, a thin film transformer 221, and output voltage regulator circuit 222 embedded in deep wells of substrate 230.

Sensorless control system and method of permanent magnet synchronous motor

Abstract: If the magnitude of a voltage command vector to a motor driver is smaller than a preset value in a control period, in each of a predetermined number of subsequent control periods (a compensation period), a pulse voltage vector is added to the voltage command vector so as to make substantially zero the average value of the added pulse voltage vectors during the compensation periods, and the compensated voltage command vector is used for the subsequent calculation. Also, two direction data for each phase winding are stored at the center of each of the two dead times following the edges of a voltage command pulse in each control period. An estimated phase voltage is calculated from the last voltage command pulse width, a phase voltage fluctuation during the two dead time of each control period and the stored direction data. The rotor position angle is precisely calculated from the estimated phase voltage.