Showing papers on "Voltage regulator published in 2010"

Apparatus, Method and System for Providing AC Line Power to Lighting Devices

Abstract: An apparatus, method and system are disclosed for providing AC line power to lighting devices such as light emitting diodes (“LEDs”). A representative apparatus comprises: a plurality of LEDs coupled in series to form a plurality of segments of LEDs; first and second current regulators; a current sensor; and a controller to monitor a current level through a series LED current path, and to provide for first or second segments of LEDs to be in or out of the series LED current path at different current levels. A voltage regulator is also utilized to provide a voltage during a zero-crossing interval of the AC voltage. In a representative embodiment, first and second segments of LEDs are both in the series LED current path regulated at a lower current level compared to when only the first segment of LEDs is in the series LED current path.

Charge Pump Circuits: An Overview on Design Strategies and Topologies

Abstract: Due to the continuous power supply reduction, charge pumps circuits are widely used in integrated circuits (ICs) devoted to several kind of applications such as smart power, nonvolatile memories, switched capacitor circuits, operational amplifiers, voltage regulators, SRAMs, LCD drivers, piezoelectric actuators, RF antenna switch controllers, etc. The main focus of this tutorial manuscript is to provide a deep understanding of the charge pumps behavior, to present useful models and key parameters and to organically and in details discuss the optimized design strategies. Finally, an overview of the main different topologies is also included.

An Output-Capacitorless Low-Dropout Regulator With Direct Voltage-Spike Detection

Abstract: An output-capacitorless low-dropout regulator (LDO) with a direct voltage-spike detection circuit is presented in this paper. The proposed voltage-spike detection is based on capacitive coupling. The detection circuit makes use of the rapid transient voltage at the LDO output to increase the bias current momentarily. Hence, the transient response of the LDO is significantly enhanced due to the improvement of the slew rate at the gate of the power transistor. The proposed voltage-spike detection circuit is applied to an output-capacitorless LDO implemented in a standard 0.35-?m CMOS technology (where VTHN ? 0.5 V and VTHP ? -0.65 V). Experimental results show that the LDO consumes 19 ?A only. It regulates the output at 0.8 V from a 1-V supply, with dropout voltage of 200 mV at the maximum output current of 66.7 mA. The voltage spike and the recovery time of the LDO with the proposed voltage-spike detection circuit are reduced to about 70 mV and 3 ?s, respectively, whereas they are more than 420 mV and 30 ?s for the LDO without the proposed detection circuit.

A 6- $\mu$ W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology

Abstract: An output-capacitorless low-dropout regulator (LDO) compensated by a single Miller capacitor is implemented in a commercial 90-nm CMOS technology. The proposed LDO makes use of the small transistors realized in nano-scale technology to achieve high stability, fast transient performance and small voltage spikes under rapid load-current changes without the need of an off-chip capacitor connected at the LDO output. Experimental result verifies that the proposed LDO is stable for a capacitive load from 0 to 50 pF (estimated equivalent parasitic capacitance from load circuits) and with load capability of 100 mA. Moreover, the gain-enhanced structure provides sufficient loop gain to improve line regulation to 3.78 mV/V and load regulation to 0.1 mV/mA, respectively. The embedded voltage-spike detection circuit enables pseudo Class-AB operation to drive the embedded power transistor promptly. The measured power consumption is only 6 μW under a 0.75-V supply. The maximum overshoot and undershoot under a 1.2-V supply are less than 66 mV for full load current changes within 100-ns edge time, and the recovery time is less than 5 μs.

Online Monitoring of Voltage Stability Margin Using an Artificial Neural Network

Abstract: In this paper, an artificial neural network (ANN) based method is developed for quickly estimating the long-term voltage stability margin. The investigation presented in the paper showed that node voltage magnitudes and the phase angles are the best predictors of voltage stability margin. Further, the paper shows that the proposed ANN based method can successfully estimate the voltage stability margin not only under normal operation but also under N-1 contingency situations. If the voltage magnitudes and phase angles are obtained in real-time from phasor measurement units (PMUs) using the proposed method, the voltage stability margin can be estimated in real time and used for initiating stability control actions. Finally, a suboptimal approach to determine the best locations for PMUs is presented. Numerical examples of the proposed techniques are presented using the New England 39-bus test system and a practical power system which consists of 1844 buses, 746 load buses, and 302 generator buses.

Rotor Angle Instability Prediction Using Post-Disturbance Voltage Trajectories

Abstract: A new method for predicting the rotor angle stability status of a power system immediately after a large disturbance is presented. The proposed two stage method involves estimation of the similarity of post-fault voltage trajectories of the generator buses after the disturbance to some pre-identified templates and then prediction of the stability status using a classifier which takes the similarity values calculated at the different generator buses as inputs. The typical bus voltage variation patterns after a disturbance for both stable and unstable situations are identified from a database of simulations using fuzzy C-means clustering algorithm. The same database is used to train a support vector machine classifier which takes proximity of the actual voltage variations to the identified templates as features. Development of the system and its performance were demonstrated using a case study carried out on the IEEE-39 bus system. Investigations showed that the proposed method can accurately predict the stability status six cycles after the clearance of a fault. Further, the robustness of the proposed method was examined by analyzing its performance in predicting the instability when the network configuration is altered.

0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS

Abstract: Digital LDO is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-µA quiescent current at 200-µA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO's, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.

Method for determining the maximum allowable penetration level of distributed generation without steady-state voltage violations

Abstract: One of the main factors that may limit the penetration level of distributed generation (DG) in typical distribution systems is the steady-state voltage rise. The maximum amount of active power supplied by distributed generators into each system bus without causing voltage violations can be determined by using repetitive power flow studies. However, this task is laborious and usually time-consuming, since different loading level and generation operation modes have to be evaluated. Therefore this article presents a method that, based on only one power flow solution and one matrix operation, can directly determine the maximum power that can be injected by distributed generators into each system bus without leading to steady-state voltage violations. This method is based on the determination of voltage sensitivities from a linearised power system model. In addition, this article proposes a numerical index to quantify the responsibility of each generator for the voltage level rise in a multi-DG system. Based on this index, utility managers can decide which generators, and in which degree, should be penalised by the voltage rise or rewarded by not depreciating the voltage profile. The method is applied to a 70-bus distribution network. The results are compared with those obtained by repetitive power flow solutions in order to validate the proposed method.

Evaluation of control and modulation methods for modular multilevel converters

Abstract: The modular multilevel converter is a promising converter technology for various high-voltage high-power applications. Despite the apparent simplicity of the circuit, the inherent dynamics of the converter and the balancing of the sub-module capacitor voltages impose high requirements on the control system, which can be implemented in quite different ways. To illustrate this, and to provide a guidance for future research on the subject, this paper presents an evaluation of four different control and modulation methods. The investigation is based on experiments on a down-scaled 10 kVA converter having 10 submodules per phase leg. The main items to be investigated are dynamics within the sub-modules, arm voltages and circulating currents. It is found that the suggested open-loop control method provides the fastest arm-voltage response and that the balancing approach based on a sorting algorithm is substantially faster and less complicated to implement than the method using a dedicated voltage controller for each sub-module.

Multilevel Optimal Predictive Dynamic Voltage Restorer

Abstract: This paper presents an optimal predictive controller for a multilevel converter-based dynamic voltage restorer (DVR), which is able to improve the voltage quality of sensitive loads connected to the electrical power network. The optimal predictive controlled multilevel DVR can restore sags and short interruptions while reducing the total harmonic distortion (THD) of the ac line voltages to values lower than 1%. The DVR is based on a three-phase neutral point clamped converter to dynamically inject a compensation voltage vector in series with the line voltage, through series-connected transformer secondary windings. To assure high-quality voltages for sensitive loads, we devise optimal predictive control laws for the injected compensation ac voltages. A suitable quadratic weighed cost functional is used to choose the voltage vector, minimizing both the ac voltage errors through current injection and the dc side capacitor voltage unbalancing. The performance of the proposed predictive controller is compared to classical proportional integral (PI): synchronous frame and stationary frame (P+resonant) controllers. The line-side filter capacitor topology is compared to the regular converter-side filter capacitor. Obtained experimental results show that the ac voltages are almost sinusoidal in steady-state operation when facing balanced and unbalanced sags and short interruptions with unbalanced loads. Voltage THD is reduced to values lower than 1%; the DVR is behaving also as a series active power filter for the ac voltages.

Mitigation of Voltage Disturbances Using Dynamic Voltage Restorer Based on Direct Converters

Abstract: In this paper, two new topologies are proposed for three-phase dynamic voltage restorers (DVRs). These topologies are based on direct converters. The proposed topologies do not require dc-link energy storage elements. As a result, they have less volume, weight, and cost. They can also compensate long-time voltage sags and swells. The proposed DVRs can compensate several types of disturbances, such as voltage sags, swells, unbalances, harmonics, and flickers. Moreover, due to the fact that the compensation voltage for each phase is taken from all three phases, the proposed topologies can compensate one-phase outages. In the proposed topologies, three independent three-phase to single-phase direct converters are used. Each converter operates independently and, as a result, the proposed DVRs properly compensate unbalanced voltage sags and swells. The used converters can be constructed by four or six power switches. Depending on the structure of the used converters, the compensation ranges will be different. A new control method is also proposed for using direct ac/ac converters. The experimental and simulation results verify the capabilities of the proposed topologies in compensation of voltage distortions.

Interphase AC–AC Topology for Voltage Sag Supporter

Abstract: A new topology is proposed in this paper to compensate voltage sags in power distribution systems. Voltage sag is one of the major power quality problems encountered by industries. The traditional voltage sag compensator, which is a dynamic voltage restorer based on energy storage device with a series-connected voltage-source inverter, is not adequate for compensating deep and long-duration voltage sags. As per the sensitive load concern, deep and long-duration sags are more vulnerable than shallow and short-duration sags. To compensate the voltage sag, a new interphase ac-ac topology is proposed that needs no storage device. The compensator of each phase is connected on the other two phases and the power is tapped from them. A single-phase compensator is realized with two ac chopper circuits and two transformers. By controlling the duty cycle of each ac chopper, the required voltage is realized to compensate the voltage sag. Analysis, simulation, and experimental results are presented to demonstrate the proposed concept.

A Low-Power Fast-Transient 90-nm Low-Dropout Regulator With Multiple Small-Gain Stages

Abstract: A power-efficient 90-nm low-dropout regulator (LDO) with multiple small-gain stages is proposed in this paper. The proposed channel-resistance-insensitive small-gain stages provide loop gain enhancements without introducing low-frequency poles before the unity-gain frequency (UGF). As a result, both the loop gain and bandwidth of the LDO are improved, so that the accuracy and response speed of voltage regulation are significantly enhanced. As no on-chip compensation capacitor is required, the active chip area of the LDO is only 72.5 μm × 37.8 μm. Experimental results show that the LDO is capable of providing an output of 0.9 V with maximum output current of 50 mA from a 1-V supply. The LDO has a quiescent current of 9.3 μA, and has significantly improvement in line and load transient responses as well as performance in power-supply rejection ratio (PSRR).

Output-Capacitor-Free Adaptively Biased Low-Dropout Regulator for System-on-Chips

Abstract: A high-precision low-voltage adaptively biased (AB) low-dropout regulator (LDR) with extended loop bandwidth is proposed. The multistage output-capacitor-free LDR is stabilized by Miller compensation and Q-reduction techniques to reduce the required minimum load current. Adaptive biasing is achieved by using direct current feedback from a simple current mirror. The dynamics of both the main feedback loop (MFL) and the adaptive biasing loop are thoroughly analyzed. Tradeoffs between the adaptive biasing factor and the MFL stability are discussed. The AB LDR is designed using a standard 0.35- ?m CMOS technology ( Vtn ? 0.52 V and Vtp ? -0.72 V). The output is 1.0 V, which delivers a maximum current of 100 mA. The minimum input voltage is 1.2 V, and the minimum load current required is reduced to 50 ?A . Extensive simulation results verify that the proposed LDR achieves high loop bandwidth, fast line and load transient responses, high power supply rejection, and low output impedance.

Global Minimization of Financial Losses Due to Voltage Sags With FACTS Based Devices

Abstract: FACTS based devices are proven to be an efficient mitigation solution for voltage sag prevention. The high cost of FACTS based devices often prohibits their wider deployment within power networks. This paper presents an approach for comprehensively assessing the financial benefits to the network resulting from their use. The annual financial losses of the entire network due to voltage sags are used as a savings target. The three most widely used FACTS based devices for voltage sag mitigation, namely, static VAr compensator (SVC), static compensator (STATCOM) and dynamic voltage restorer (DVR) are then optimally placed using a Niching genetic algorithm (NGA). The aim is to reduce overall financial losses in the network due to voltage sags. The cost of the individual devices along with their installation costs and annual maintenance are taken into account in the optimization procedure. Since this methodology is largely based on an economic evaluation of the solution, several conventional economic analysis methods are utilized. Simulations are performed on a 295-bus generic distribution network (GDN).

Implementation and Performance Evaluation of a Fast Dynamic Control Scheme for Capacitor-Supported Interline DVR

Abstract: The implementation of a fast dynamic control scheme for capacitor-supported interline dynamic voltage restorer (DVR) is presented in this paper. The power stage of the DVR consists of three inverters sharing the same dc link via a capacitor bank. Each inverter has an individual inner control loop for generating the gate signals for the switches. The inner loop is formed by a boundary controller with second-order switching surface, which can make the load voltage ideally revert to the steady state in two switching actions after supply voltage sags, and also gives output of low harmonic distortion. The load-voltage phase reference is common to all three inner loops and is generated by an outer control loop for regulating the dc-link capacitor voltage. Such structure can make the unsagged phase(s) and the dc-link capacitor to restore the sagged phase(s). Based on the steady-state and small-signal characteristics of the control loops, a set of design procedures will be provided. A 1.5-kVA, 220-V, 50-Hz prototype has been built and tested. The dynamic behaviors of the prototype under different sagged and swelled conditions and depths will be investigated. The quality of the load voltage under unbalanced and distorted phase voltages, and nonlinear inductive loads will be studied.

Modeling of FACTS Devices for Voltage Sag Mitigation Studies in Large Power Systems

Abstract: Flexible ac transmission system (FACTS) devices or their subderivative custom power devices are efficient and often used and recommended power-electronics-based devices for mitigation of voltage sags in electrical power system. With FACTS devices installed, the overall system (and individual bus) sag performance could significantly change depending on the type of the device used. In order to assess this change in sag performance in realistic large power systems, the classical (essentially static) fault calculation procedure should be amended to incorporate the effects of these devices on bus voltages. This paper presents a new approach of quasistatic sag analysis using a system impedance (Z _bus) matrix that incorporates FACTS devices. Three types of FACTS devices which are most often used in practical applications are considered in this study: static compensator, static var compensator, and the dynamic voltage restorer. The case studies based on the 295-bus generic distribution system are used to illustrate the modeling method and the effectiveness of these devices in sag mitigation.

Reverse Nested Miller Compensation Using Current Buffers in a Three-Stage LDO

Abstract: A novel frequency compensation scheme called reverse nested Miller compensation using current buffers (RNMCCB) for three-stage amplifiers is proposed. As opposed to previous reverse nested schemes, our work uses inverting gain stages for both the second and third stages. The outer compensation loop utilizes a current mirror as an inverting current buffer (CB), and the inner loop uses a common-gate amplifier as a CB, creating two left-half-plane (LHP) zeros. We introduce a simple and effective method of placing a resistor in series with a CB for accurate placement of LHP zeros. As a design example of the RNMCCB scheme, we propose a three-stage low dropout voltage regulator (LDO) in a 0.5-?m CMOS process to supply 1.21 V to a load ranging from 1 ?A to 100 mA. Our design goals were to simultaneously achieve very high current efficiency and very low transient output voltage variation. As such, we achieved a 99.95% current efficiency and a maximum load transient output voltage variation of ±48 mV with an output capacitor of 100 nF. Experimental results, in good agreement with theoretical analysis, validate the novel RNMCCB frequency compensation scheme.

Predictive control of a three-phase UPS inverter using two steps prediction horizon

Abstract: A Model Predictive Control scheme is used for voltage control in a three-phase inverter with output LC filter. The controller uses a model of the system to calculate predictions of the future value of the system variables for a given voltage vector sequence. A cost function considering the voltage errors is defined and the voltage vectors that minimize it are selected and applied in the converter. The effect of considering different number of prediction steps is studied in this work in terms of THD. Simulation results for one and two prediction steps are presented and compared.

Multiobjective Optimization and Fuzzy Logic Applied to Planning of the Volt/Var Problem in Distributions Systems

Abstract: This paper deals with integrated voltage and reactive power control (volt/var) for radial distribution feeders in planning issues, by means of the application of automatic voltage regulators (AVRs) banks and capacitors. A multiobjective genetic algorithm (SPEA2) improved using fuzzy logic is presented to solve the volt/var problem, since it is a combinatorial multiobjective optimization problem. The expert knowledge is taken into account via fuzzy logic in order to reduce the search space using voltage regulators in standard units. According to the multiobjective optimization fundamentals, an optimal solution ensemble is obtained, which concomitantly represents the solutions to both objectives, in such way that the operational restrictions of systems are satisfied. The algorithm is evaluated for a known 69-bus feeder in the literature of the subject. The obtained results demonstrate that the proposed method provides good concordance between the obtained solution and the Pareto front.

A Proportional ${\bm +}$ Multiresonant Controller for Three-Phase Four-Wire High-Frequency Link Inverter

Abstract: A new solution for unbalanced and nonlinear loads in terms of power circuit topology and controller structure is proposed in this paper. A three-phase four-wire high-frequency ac-link inverter is adopted to cater to such loads. Use of high-frequency transformer results in compact and light-weight systems. The fourth wire is taken out from the midpoint of the isolation transformer in order to avoid the necessity of an extra leg. This makes the converter suitable for unbalanced loads and eliminates the requirements of bulky capacitor in half-bridge inverter. The closed-loop control is carried out in stationary reference frame using proportional + multiresonant controller (three separate resonant controller for fundamental, fifth and seventh harmonic components). The limitations on improving steady-state response of harmonic resonance controllers is investigated and mitigated using a lead-lag compensator. The proposed voltage controller is used along with an inner current loop to ensure excellent performance of the power converter. Simulation studies and experimental results with 1 kVA prototype under nonlinear and unbalanced loading conditions validate the proposed scheme.

Class resonant-H electrosurgical generators

Abstract: A generator for use with an electrosurgical device is provided. The generator has a gain stage electrically disposed between a first voltage rail and a second voltage rail, wherein the gain stage includes an input and an output. A voltage source operably coupled to the gain stage input and configured to provide an input signal thereto responsive to a drive control signal is also provided. The generator also has one or more sensors configured to sense an operational parameter of the amplifier and to provide a sensor signal corresponding thereto and a controller adapted to receive the sensor signal(s) and in response thereto provide a drive control signal to the voltage source. The generator has an amplifier output configured to supply an output voltage corresponding to the first voltage rail and the second voltage rail when the output of the gain stage falls between a voltage of the first voltage rail and a voltage of the second voltage rail and is configured to supply a peak voltage output when the voltage output is falls greater than the voltage of the first voltage rail or less than the voltage of the second voltage rail.

Fast sag/swell detection method for fuzzy logic controlled dynamic voltage restorer

Abstract: In this study, the design and analysis of a fuzzy logic (FL) controlled dynamic voltage restorer (DVR) are presented and extended to perform fast fault detection. A new control method for DVR is proposed by combining FL with a carrier modulated PWM inverter. The proposed control scheme is simple to design and has excellent voltage compensation capabilities. The proposed method for voltage sag/swell detection has the ability of detecting different kinds of power disturbances faster than conventional detection methods. Effectiveness of the proposed detection method is shown by comparison with the conventional methods in the literature. Simulation results under unbalanced supply voltage are presented to evaluate the performance of the designed DVR.

Global Voltage Sag Mitigation With FACTS-Based Devices

Abstract: This paper presents an approach to optimally select and allocate flexible ac transmission (FACTS) devices in a distribution network in order to minimize the number of voltage sags at network buses. The method proposed is based on the optimization of a preselected objective function using simple and niching genetic algorithms (GA). The objective of the optimization is to achieve the improvement in overall system sag performance of the network. Using proposed GA-based optimization, the location, the type and the rating of six (in total) FACTS devices are optimized simultaneously. Three types of FACTS devices are implemented in this study, namely, static var compensator, static compensator, and dynamic voltage restorer. The performance of the proposed algorithm is tested and illustrated on 295-bus generic distribution system.

Device, circuit and system-level analysis of noise in multi-bit phase-change memory

Abstract: We present a comprehensive investigation of noise in multi-bit phase-change memory (PCM). The impact of noise on data integrity was quantified with a combination of experiments and simulations. A prototype chip was fabricated to support our system-level analysis, which shows that a raw bit error rate of ∼10−4 is achievable at 3-bit/cell. At the circuit level, we identified the bit line capacitance and the voltage regulator noise as the critical elements determining the electronic readout circuit noise. In addition, device-level measurements showed that 80% of the total noise can be traced back to the fluctuations in the PCM cell current itself. Our analysis captures for the first time how these fluctuations ultimately limit the achievable bit error rate in future multi-level-cell (MLC) PCM chips.

High Power-Supply-Rejection (PSR) Current-Mode Low-Dropout (LDO) Regulator

Abstract: Modern system-on-a-chip (SoC) solutions suffer from limited on-chip capacitance, which means that the switching events of functionally dense ICs induce considerable noise in the supplies. This ripple worsens the accuracy of sensitive analog electronics, such as ADCs, PLLs, and VCOs, etc. Without dropping a substantial voltage, point-of-load (PoL) low-dropout (LDO) regulators reduce (filter) this noise but only as much as their loop gains and bandwidths allow. This brief presents a 5-mA 1.5-μm bipolar current-mode LDO regulator that, with a higher bandwidth current loop, suppresses higher frequency noise by 49 dB (i.e., power-supply rejection) up to 10 MHz with only 68 nF at the output, which is 20 dB better than its voltage-mode counterpart.

SMES Based Dynamic Voltage Restorer for Voltage Fluctuations Compensation

Abstract: This paper presents a superconducting magnetic energy storage (SMES) based dynamic voltage restorer (DVR) to protect consumers from the grid voltage fluctuations. Due to the characteristic of high energy density and quick response, a superconducting magnet is selected as the energy storage unit to improve the compensation capability of DVR. This paper analyses the operation principle of the SMES based DVR, and designs the DVR output voltage control method. The control system mainly consists of two parts, the PWM converter controller and the DC/DC chopper controller. The PWM converter controller adopts double-loop control strategy, with an inner current regulator and an outer voltage controller. Combining the coordinated control of DC/DC chopper, the DVR can regulate output voltage accurately and quickly to compensate the system voltage fluctuations. Using MATLAB SIMULINK, the models of the SMES based DVR is established, and the simulation tests are performed to evaluate the system performance.

Light emitting diode array driving apparatus

Abstract: There is provided a LED array driving apparatus for driving a light emitting array having a plurality of LEDs connected to one another, including: a DC-DC converting part; a current/voltage detecting part detecting a magnitude of a first current flowing through a switching transistor of the DC-DC current converting part to correspondingly output a first current detection voltage, detecting a magnitude of a both-end voltage of the LED array to correspondingly output a LED array detection voltage, and detecting a magnitude of a current flowing through the LED array to correspondingly output a second current detection voltage; and a constant current controlling part controlling an on/off duty of the switching transistor according to the magnitude of the first current detection voltage, the second current detection voltage and the LED array detection voltage detected by the current/voltage detecting part.

Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation

Abstract: Integrating a large number of on-chip voltage regulators holds the promise of solving many power delivery challenges through strong local load regulation and facilitates systemlevel power management. The quantitative understanding of such complex power delivery networks (PDNs) is hampered by the large network complexity and interactions between passive on-die/package-level circuits and a multitude of nonlinear active regulators. We develop a fast combined GPU-CPU analysis engine encompassing several simulation strategies, optimized for various subcomponents of the network. Using accurate quantitative analysis, we demonstrate the significant performance improvement brought by on-chip low-dropout regulators (LDOs) in terms of suppressing high-frequency local voltage droops and avoiding the mid-frequency resonance caused by off-chip inductive par-asitics. We perform comprehensive analysis on the tradeoffs among overhead of on-chip LDOs, maximum voltage droop and overall power efficiency. We conduct systematic design optimization by developing a simulation-based nonlinear optimization strategy that determines the optimal number of on-chip LDOs required and on-board input voltage, and the corresponding voltage droop and power efficiency for PDNs with multiple power domains.

Digital hybrid V2 control for buck converters

Abstract: Stabilization of a switching voltage regulator employing V2 control against ripple oscillation instability when the equivalent series resistance (ESR) of an output capacitor is small is provided by providing both an external ramp and an internal ramp (only the latter of which requires an approximation of inductor current) in the control feedback path, preferably including both inner and outer feedback loops. Approximation of inductor current using such an arrangement is non-critical and may be estimated based on power input voltage. Drift of a circuit providing such an inductor current estimation is preferably avoided by adjusting control duty cycle or slew rate of the positive-going ramp portion of the estimated inductor current triangular waveform.