Showing papers on "Voltage regulator published in 2016"

Droop-Free Distributed Control for AC Microgrids

Abstract: A cooperative distributed secondary/primary control paradigm for AC microgrids is proposed. This solution replaces the centralized secondary control and the primary-level droop mechanism of each inverter with three separate regulators: voltage, reactive power, and active power regulators. A sparse communication network is spanned across the microgrid to facilitate limited data exchange among inverter controllers. Each controller processes its local and neighbors' information to update its voltage magnitude and frequency (or, equivalently, phase angle) set points. A voltage estimator finds the average voltage across the microgrid, which is then compared to the rated voltage to produce the first-voltage correction term. The reactive power regulator at each inverter compares its normalized reactive power with those of its neighbors, and the difference is fed to a subsequent PI controller that generates the second-voltage correction term. The controller adds the voltage correction terms to the microgrid rated voltage (provided by the tertiary control) to generate the local voltage magnitude set point. The voltage regulators collectively adjust the average voltage of the microgrid at the rated voltage. The voltage regulators allow different set points for different bus voltages and, thus, account for the line impedance effects. Moreover, the reactive power regulators adjust the voltage to achieve proportional reactive load sharing. The third module, the active power regulator, compares the local normalized active power of each inverter with its neighbors' and uses the difference to update the frequency and, accordingly, the phase angle of that inverter. The global dynamic model of the microgrid, including distribution grid, regulator modules, and the communication network, is derived, and controller design guidelines are provided. Steady-state performance analysis shows that the proposed controller can accurately handle the global voltage regulation and proportional load sharing. An AC microgrid prototype is set up, where the controller performance, plug-and-play capability, and resiliency to the failure in the communication links are successfully verified.

Sensor-Less Five-Level Packed U-Cell (PUC5) Inverter Operating in Stand-Alone and Grid-Connected Modes

Abstract: In this paper, a new mode of operation has been introduced for packed U-cell (PUC) inverter. A sensor-less voltage control based on redundant switching states is designed for the five-level packed U-cell (PUC5) inverter, which is integrated into switching process. The sensor-less voltage control is in charge of fixing the dc capacitor voltage at half of the dc source value results in generating symmetric five-level voltage waveform at the output with low harmonic distortion. The sensor-less voltage regulator reduces the complexity of the control system, which makes the proposed converter appealing for industrial applications. An external current controller has been applied for grid-connected application of the introduced sensor-less PUC5 to inject active and reactive power from inverter to the grid with arbitrary power factor, while the PUC auxiliary dc bus is regulated only by sensor-less controller combined with new switching pattern. Experimental results obtained in stand-alone and grid-connected operating modes of proposed PUC5 inverter prove the fast response and good dynamic performance of the designed sensor-less voltage control in balancing the dc capacitor voltage at desired level.

Voltage Dynamics of Current Control Time-Scale in a VSC-Connected Weak Grid

Abstract: Voltage problems are challenging in modern power systems with a high penetration of renewables integrated via power electronics. This paper extends the transient time-scale classification to identify voltage dynamics in modern power systems. Voltage dynamics in the current control time-scale is firstly proposed and then the mechanism of terminal voltage change is elaborated. After that the significant influences of the voltage source converter (VSC), current control (CC) loop and voltage feed forward (VFF) on the voltage dynamics in the current control time-scale are discussed. The VSC current control loop provides positive damping on the terminal voltage, while the VFF scheme results in an additional loop that deteriorates terminal voltage dynamic performance and stability. In addition, a sensitivity analysis was carried out to investigate the influence of critical parameters on stability. Finally, simulation results of a current-controlled VSC attached to different strength of AC grids (including a weak grid) are presented to validate the phenomenon and the influencing factors of voltage dynamics in the current control time-scale.

Comparison of a Buck Converter and a Series Capacitor Buck Converter for High-Frequency, High-Conversion-Ratio Voltage Regulators

Abstract: This paper presents an analytical and experimental comparison of a two-phase buck converter and a two-phase, series capacitor buck converter. The limitations of a conventional buck converter in high-current (10 A or more), and high-frequency (HF, 3–30 MHz) point-of-load voltage regulators with large voltage conversion ratios (10-to-1) are highlighted. The series capacitor buck converter exhibits desirable characteristics at HF, including lower switching loss, less inductor current ripple, automatic phase current balancing, duty ratio extension, and soft charging of the energy transfer capacitor. Analysis of the topologies indicates that switching loss and inductor core loss can dominate at HF. Results from side-by-side 12 V input, 1.2 V output hardware prototypes demonstrate that the series capacitor buck converter has up to 12 percentage points higher efficiency at 3 MHz and reduces power loss by up to 33% at full load (10 A). Some guidelines for inductor selection are provided, and a switch stress comparison reveals that the maximum converter switch stress is reduced by 30%.

High Step-Up/Step-Down Soft-Switching Bidirectional DC–DC Converter With Coupled-Inductor and Voltage Matching Control for Energy Storage Systems

Abstract: A soft-switching bidirectional dc–dc converter (BDC) with a coupled-inductor and a voltage doubler cell is proposed for high step-up/step-down voltage conversion applications. A dual-active half-bridge (DAHB) converter is integrated into a conventional buck-boost BDC to extend the voltage gain dramatically and decrease switch voltage stresses effectively. The coupled inductor operates not only as a filter inductor of the buck-boost BDC, but also as a transformer of the DAHB converter. The input voltage of the DAHB converter is shared with the output of the buck-boost BDC. So, PWM control can be adopted to the buck-boost BDC to ensure that the voltage on the two sides of the DAHB converter is always matched. As a result, the circulating current and conduction losses can be lowered to improve efficiency. Phase-shift control is adopted to the DAHB converter to regulate the power flows of the proposed BDC. Moreover, zero-voltage switching (ZVS) is achieved for all the active switches to reduce the switching losses. The operational principles and characteristics of the proposed BDC are presented in detail. The analysis and performance have been fully validated experimentally on a 40–60 V/400 V 1-kW hardware prototype.

Adaptive DC-Link Voltage Control of Two-Stage Photovoltaic Inverter During Low Voltage Ride-Through Operation

Abstract: This paper proposes an adaptive dc-link voltage control method for the two-stage photovoltaic inverter during the low voltage ride-through (LVRT) operation period. The dc-link voltage will be controlled to follow the change of grid voltage during the LVRT operation to maintain the high modulation ratio so that the high frequency harmonics injected into the grid can be attenuated significantly. Besides, when suffering the asymmetrical grid faults, the proposed control method could to some extent attenuate the double-line-frequency dc-link voltage ripple to keep the dc-link voltage in the safe operational range by shifting the double-line-frequency power ripple to the front-end dc input source, which can be achieved by intentionally fluctuating the dc input power or employing a bidirectional dc–dc converter depending on the voltage drop ratio and the input power level. The theoretical findings were verified by MATLAB simulations and the constructed experimental prototype.

DC-Bus Voltage Control Stability Affected by AC-Bus Voltage Control in VSCs Connected to Weak AC Grids

Abstract: With the wide application of voltage source converters (VSCs) in power system, dc-bus voltage control instabilities increasingly occurred in practical conditions, especially in weak ac grid, which poses challenges on stability and security of power converters applications. This paper aims to give physical insights into the stability of dc-bus voltage control affected by ac-bus voltage control in VSC connected to weak grid. The concepts of damping and restoring components are developed for dc-bus voltage to describe the stability of dc-bus voltage control. The impact of ac-bus voltage control on dc-bus voltage control stability can be revealed by investigating the impact of ac-bus voltage control on damping and restoring components essentially. Furthermore, the detailed analysis for the impact of ac-bus voltage control on damping and restoring components is presented considering varied ac system strengths, operating points, and ac-bus voltage control parameters. The simulation results from 1.5-MW full-capacity wind power generation system are demonstrated which conform well to the analysis. Finally, the experimental results validate the analysis.

Control Strategies of Three-Phase Distributed Generation Inverters for Grid Unbalanced Voltage Compensation

Abstract: The high penetration level of power electronics interfaced distributed generation (DG) systems creates great ancillary services potential through the DG interfacing converters, such as the grid unbalanced voltage compensation. However, the unbalanced voltage compensation may cause adverse effects on the DGs' operation, such as output active power oscillation and dc-link voltage variations. Moreover, since the compensation is realized through the available rating of DGs' interfacing converters, it is equally important to consider the effectiveness of control strategy for unbalanced voltage compensation. Considering these challenging issues, two grid unbalanced voltage compensation strategies for three-phase power electronics interfaced DG systems are proposed in this paper. Especially, the first control strategy aims at minimizing the DG's active power oscillation and reducing the adverse effects of unbalanced voltage compensation on DG's operation. The second control strategy focuses on the effectiveness of unbalanced voltage compensation by controlling DG's negative sequence current to be inphase with the grid negative sequence current. Performances of the two proposed control strategies under different grid conditions and DG operating conditions are studied, and recommendations for appropriate control strategy utilization under various conditions are provided. Finally, validity of the proposed strategies is verified by both simulations and experimental results.

A Novel High Step-Up Dual Switches Converter With Coupled Inductor and Voltage Multiplier Cell for a Renewable Energy System

Abstract: A novel high step-up converter, which is suitable for a renewable energy system, is proposed in this paper. The proposed converter is composed of the dual switches structure, three-winding coupled inductor, and two voltage multiplier cells in order to achieve the high step-up voltage gain. The dual switches structure is beneficial to reduce the voltage stress and current stress of the switch. In addition, two multiplier capacitors are, respectively, charged during the switch-on period and switch-off period, which increases the voltage conversion gain. Meanwhile, the energy stored in the leakage inductor is recycled with the use of clamped capacitors. Thus, two main power switches with low on-resistance and low current stress are available. As the leakage inductor, diode reverse-recovery problem is also alleviated. Therefore, the efficiency is improved. This paper illustrates the operation principle of the proposed converter; discusses the effect of the leakage inductor; analyzes the influence of parasitic parameters on the voltage gain and efficiency, the voltage stresses and current stresses of power devices are shown; and a comparison between the performance of the proposed converter and the previous high step-up converters is performed. Finally, the prototype circuit with input voltage 20 V, output voltage 200 V, and rated power 200 W is operated to verify its performance.

Real-Time Implementation of a Seven-Level Packed U-Cell Inverter with a Low-Switching-Frequency Voltage Regulator

Abstract: In this paper, a new cascaded nonlinear controller has been designed and implemented on the packed U-cell (PUC) seven-level inverter. The proposed controller has been designed based on a simplified model of PUC inverter and consists of a voltage controller as an outer loop and a current controller as an inner loop. The outer loop regulates the PUC inverter capacitor voltage as the second dc bus. The inner loop is in charge of controlling the flowing current, which is also used to charge and discharge that capacitor. The main goal of the whole system is to keep the dc capacitor voltage at a certain level results in generating a smooth and quasi-sine-wave seven-level voltage waveform at the output of the inverter with low switching frequency. The proposed controller performance is verified through experimental tests. Practical results prove the good dynamic performance of the controller in fixing the PUC capacitor voltage for various and variable load conditions and yet generating low-harmonic seven-level voltage waveform to deliver power to the loads. Operation as an uninterruptible power supply (UPS) or ac loads interface for photovoltaic energy conversion applications is targeted.

Distributed adaptive droop control for DC distribution systems

Abstract: A distributed-adaptive droop mechanism is proposed for secondary/primary control of dc microgrids. The conventional secondary control that adjusts the voltage set point for the local droop mechanism is replaced by a voltage regulator. A current regulator is also added to fine-tune the droop coefficient for different loading conditions. The voltage regulator uses an observer that processes neighbors' data to estimate the average voltage across the microgrid. This estimation is further used to generate a voltage correction term to adjust the local voltage set point. The current regulator compares the local per-unit current of each converter with the neighbors' on a communication graph and, accordingly, provides an impedance correction term. This term is then used to update the droop coefficient and synchronize per-unit currents or, equivalently, provide proportional load sharing. The proposed controller precisely accounts for the transmission/distribution line impedances. The controller on each converter exchanges data with only its neighbor converters on a sparse communication graph spanned across the microgrid. Global dynamic model of the microgrid is derived with the proposed controller engaged. A low-voltage dc microgrid prototype is used to verify the controller performance, link-failure resiliency, and the plug-and-play capability.

A Novel SVPWM Algorithm for Five-Level Active Neutral-Point-Clamped Converter

Abstract: The five-level active neutral-point-clamped (5L-ANPC) converter is becoming an attractive topology of multilevel converter family. A novel SVPWM algorithm based on line voltage coordinate was studied in this paper to overcome shortcomings of the traditional algorithm. Through coordinate transformation, steps of determining the basic vectors and the solution about the basic vector corresponding action time are simplified. Combining with the characteristics of 5L-ANPC converter and the new control algorithm, a method of controlling the voltage balancing of dc-link capacitors and floating-capacitors is proposed. According to the voltage of dc-link capacitors, the suitable switching sequence which can balance the voltage of dc-link capacitors is chosen. The high common-mode voltage will affect the service life of motor and reduce the reliability of the system especially in high-voltage converter. The common-mode voltage is also reduced by choosing the right switching state in this paper. The validity of the proposed method was proved by the experimental results.

An Active Cross-Connected Modular Multilevel Converter (AC-MMC) for a Medium-Voltage Motor Drive

Abstract: This paper presents an active cross-connected modular multilevel converter (AC-MMC) based on series-connected half-bridge modules. It is intended for completely enhancing the performance of a medium-voltage motor drive system in the full speed range from standstill to rated speed under all load conditions. The proposed AC-MMC circuit is characterized by the cross connection of upper and lower arm middle taps through a branch of series-connected half-bridge converters, which have an identical voltage and current rating with the submodules in the upper and lower arms. This cross-connected branch provides a physical power transfer channel for the upper and lower arms. By properly controlling the amount of high-frequency current flowing through the cross-connected branch, the power balance between the upper and lower arms is achieved even at a zero/low motor speed under constant torque condition. Meanwhile, no common-mode voltage is introduced in the whole speed range. A control strategy with focus on submodule capacitor voltage control is also proposed in this paper to guarantee the normal converter operation. Simulation results obtained from a 4160-V, 1-MW model verify the feasibility of the proposal. Experiments on a downscaled prototype also confirm the validity of the novel circuit and the associated control strategy.

A Subthreshold ARM Cortex-M0+ Subsystem in 65 nm CMOS for WSN Applications with 14 Power Domains, 10T SRAM, and Integrated Voltage Regulator

Abstract: The Internet of Things (IoT) is widely predicted to comprise billions of connected devices, many of which will be wireless sensor nodes (WSN). Energy efficiency is a huge challenge here, followed by node cost and ease of software (SW) development. Addressing all of the above, this paper presents an 11.7 pJ/cycle subthreshold ARM Cortex-M0+ WSN processing subsystem implemented in low-leakage 65 nm CMOS. Voltage and frequency scalability is from 850 nW active power at 250 mV to 66 MHz above 900 mV, with a fully integrated 82% peak-efficiency voltage regulator for direct-battery operation, and supporting 80 nW CPU and RAM state-retention power gating for SW transparent leakage reduction. SW and system optimization approaches are described and a $2.94\;\boldsymbol{\upmu}{\text{W}}$ SW ECG workload is presented.

A brief review on multi level inverter topologies

Abstract: In this paper a brief review on different multilevel inverter topologies are discussed. Inverter is a power electronic device that converts DC power into AC power at desired output voltage and frequency. Multilevel Converters nowadays have become an interesting area in the field of industrial applications. Conventional power electronic converters are able to produce an output voltage that switches between two voltage levels only. Multilevel Inverter generates a desired output voltage from several DC voltage levels at its input. The input side voltage levels are usually obtained from renewable energy sources, capacitor voltage sources, fuel cells etc. The different multilevel inverter topologies are: Cascaded H-bridges converter, Diode clamped inverter, and Flying capacitor multilevel inverter. Multilevel inverters nowadays are used for medium voltage and high power applications. The different field of applications include its use as UPS, High voltage DC transmission, Variable Frequency Drives, in pumps, conveyors etc. The disadvantages of MLI are the need for isolated power supplies, design complexity and switching control circuits.

On Coordinated Control of OLTC and Reactive Power Compensation for Voltage Regulation in Distribution Systems With Wind Power

Abstract: Active management strategies such as coordinated on load tap changer (OLTC) voltage control and reactive power compensation (RPC) are frequently suggested for voltage regulation in a distribution system with a high level of distributed generation (DG). This paper proposes a control and coordination algorithm for these two active management strategies. Voltage control through OLTC is achieved by using state estimation (SE) to determine the voltage in the network. To lower the implementation cost of the proposed control strategy, pseudo-measurements are used together with real-time measurement data in the SE. Moreover, the deadband of the automatic voltage control (AVC) relay is relaxed so that the AVC relay acts on the network’s maximum or minimum voltage obtained through the SE. This is found to be simpler to realize than adjusting the set point of the AVC relay. Voltage control through RPC is actualized by using integral controllers implemented locally at the wind turbine site. Furthermore, RPC from the local wind turbine is also used to mitigate an overvoltage at a remote bus on the same feeder when the remote wind turbine reaches its regulation limit. The applicability of the proposed voltage regulation algorithm is successfully demonstrated using a case study system.

A Three-Phase Grid Tied SPV System With Adaptive DC Link Voltage for CPI Voltage Variations

Abstract: This paper deals with a three-phase two-stage grid tied SPV (solar photo-voltaic) system. The first stage is a boost converter, which serves the purpose of MPPT (maximum power point tracking) and feeding the extracted solar energy to the DC link of the PV inverter, whereas the second stage is a two-level VSC (voltage source converter) serving as PV inverter which feeds power from a boost converter into the grid. The proposed system uses an adaptive DC link voltage which is made adaptive by adjusting reference DC link voltage according to CPI (common point of interconnection) voltage. The adaptive DC link voltage control helps in the reduction of switching power losses. A feed forward term for solar contribution is used to improve the dynamic response. The system is tested considering realistic grid voltage variations for under voltage and over voltage. The performance improvement is verified experimentally. The proposed system is advantageous not only in cases of frequent and sustained under voltage (as in the cases of far radial ends of Indian grid) but also in case of normal voltages at CPI. The THD (total harmonics distortion) of grid current has been found well under the limit of an IEEE-519 standard.

A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity

Abstract: A self-referenced VCO-based temperature sensor with reduced supply sensitivity is presented. The proposed sensor converts temperature information to frequency and then into digital bits. A novel sensing technique is proposed in which temperature information is acquired by evaluating the ratio of the output frequencies of two ring oscillators, designed to have different temperature sensitivities, thus avoiding the need for an external frequency reference. Reduced supply sensitivity is achieved by employing the voltage dependence of junction capacitance, thus avoiding the overhead of a voltage regulator. Fabricated in a 65 nm CMOS process, the prototype can operate with supply voltages ranging from 0.85 V to 1.1 V. It achieves supply sensitivity of 0.034 °C/mV and an inaccuracy of ±0.9 °C and ±2.3 °C from 0 to 100 °C after 2-point calibration, with and without static nonlinearity correction, respectively. The proposed sensor achieves 0.3 °C resolution, and a resolution FoM of 0.3 nJK2. The prototype occupies a die area of 0.004 mm2.

Flexible Control of Power Flow in Multiterminal DC Grids Using DC–DC Converter

Abstract: This paper proposes an efficient control framework that utilizes dc-dc converters to achieve flexible power flow control in multiterminal dc (MTDC) grids. The dc-dc converter employed in this paper is connected in cascade with the dc transmission line, and is therefore named cascaded power flow controller (CPFC). In this paper, a two-layer control strategy is developed for the operation and control of voltage source converter stations and CPFC station in MTDC grids. At the primary control layer, a novel differential voltage droop control is developed, while at the secondary control layer, a modified dc power flow algorithm—employing the new CPFC framework—is implemented. The overall control strategy enables the CPFC to regulate the power flow in the dc transmission line. The primary control guarantees the transient stability of the CPFC, and the secondary control system ensures the desired steady-state operation. The proposed voltage droop control framework helps the MTDC grid to remain stable in the event of a communication failure between the primary and secondary control layers. Static analysis and dynamic simulations are performed on the CIGRE B4 dc grid test system, in order to confirm the effectiveness of the proposed control framework for power flow regulation in MTDC grids.

A Design of a Wireless Power Receiving Unit With a High-Efficiency 6.78-MHz Active Rectifier Using Shared DLLs for Magnetic-Resonant A4 WP Applications

Abstract: This paper presents a full-CMOS wireless power receiving unit (WPRU) with a high-efficiency 6.78-MHz active rectifier and a dc–dc converter for magnetic-resonant alliance for wireless power (A4WP) applications. The proposed high-efficiency active rectifier with delay-locked loop (DLL) is a highly efficient receiver circuit intended for use in resonant wireless charging applications with a resonant frequency of 6.78 MHz. Each MOSFET of the proposed rectifier is turned on and off based on the ac input voltage. The delay between the ac input current and the ac input voltage due to the delays of internal blocks such as voltage limiter, level shifter, gate driver, and comparator will cause the reverse leakage current, degrading the power efficiency. Thus, the proposed active rectifier adopts the DLL to compensate for the delay caused by internal blocks, which leads to the removal of reverse leakage current and the power efficiency maximization. Moreover, to maximize power efficiency, negative impedance circuit (NIC) is also adopted to minimize switching loss. In the case of dc–dc converter, phase-locked loop is adopted for the constant switching frequency in process, voltage, and temperature (PVT) variation to solve the efficiency reduction problem, especially by heat. This chip is implemented using 0.18 μm BCD technology with an active area of 3.5 mm × 3.5 mm. When the magnitude of the ac input voltage is 8.95 V, the maximum efficiencies of the proposed active rectifier and dc–dc converter are 91.5% and 92.7%, respectively. The range of ac input voltage is 3–20 V, and the efficiency of the WPRU is about 80.86%.

Voltage Balancing Control of a Four-Level Hybrid-Clamped Converter Based on Zero-Sequence Voltage Injection Using Phase-Shifted PWM

Abstract: Four-level hybrid-clamped (4L-HC) inverter is a newly proposed topology which is suitable for high-performance medium-voltage drives. Each phase of this topology consists of eight switches and a flying capacitor and the dc-link is split into three parts by two neutral points. In order to ensure the topology operating properly, the voltages across the flying capacitors and three dc-link capacitors should be controlled and maintain balanced at their nominal values. This paper presents a decoupled voltage balancing method for this 4L-HC inverter, including the voltage balancing of dc-link capacitors and flying capacitors. A modified phase-shifted pulse-width modulation method is used to regulate the voltages of flying capacitors and the central dc-link capacitor. The relationship between the neutral-point currents and the output voltage is studied and the upper and lower dc-link capacitor voltages are balanced by injecting an optimum zero-sequence voltage. Simulation and experimental results are presented to verify the validity of this method.

Package Inductors for Intel Fully Integrated Voltage Regulators

Abstract: Intel fourth-generation and fifth-generation Core microprocessors are powered by high-frequency integrated switching voltage regulators. The inductors required to implement these regulators are constructed using the routing layers of conventional organic flip chip packaging. This paper provides an overview of the construction of these inductors including representative results from production packages. Measured inductors reported in this paper span from 1 to 6.7 nH under 2.4 mm2 and achieve $Q$ of up to 24 at 140 MHz (the switching frequency).

A review on voltage control methods using on-load tap changer transformers for networks with renewable energy sources

Abstract: Voltage control is an important method for regulating the feeder voltages in a distribution network. Various voltage control methods are used by distribution network operators (DNOs) in order to maintain the network voltages to be within an acceptable voltage level. Traditionally, on-load tap changer (OLTC) and automatic voltage control (AVC) relays are often employed in regulating the network voltages. However, the traditional voltage control techniques are no longer suitable when renewable energy (RE) sources are connected to the network because of the possibility of bidirectional power flows. The presence of reverse power flow will affect the feeder voltage profiles and influence the voltage control scheme practiced in the distribution system. This paper presents an overview on the various OLTC voltage control schemes which are used to control the voltage in distribution networks containing RE sources.

A 0.45-to-1.2-V Fully Digital Low-Dropout Voltage Regulator With Fast-Transient Controller for Near/Subthreshold Circuits

Abstract: A low quiescent current digital low-dropout (D-LDO) voltage regulator with fast-transient response time is proposed for self-powered wireless sensor applications operating at near/subthreshold supply voltage. The D-LDO regulator incorporates both hill-climbing and binary search algorithms (HCBS) in the control logic, thus leveraging on each other's strengths to minimize the output voltage's ripple and the quiescent current during the steady-state period as well as output voltage's spike and response time during the transition period. Additional features such as hysteresis mode control and freeze mode control are incorporated into the system to improve the performance of the D-LDO regulator. A dynamic comparator is proposed for the near/subthreshold supply voltage operation, which minimizes the voltage error and improves the maximum operating frequency. Fabricated in 130-nm CMOS technology, the D-LDO regulator regulates the output voltage ${V}_{{\rm OUT}}$ from 350 to 1150 mV, while the input supply voltage ${V}_{\text{IN}}$ ranges from 450 to 1200 mV. At a ${V}_{{\rm OUT}}$ of 450 mV, ${V}_{{\rm IN}}$ of 500 mV and an operating frequency of 10 MHz, the regulator delivers 1500- ${\mu }$ A load current with $I_{\text{QUIESCENT}}$ of 8.9 ${\mu }$ A and a transient response time of 1.6 ${\mu }$ s. The maximum current and power efficiencies reach 99.9% and 89.9%, respectively. The measured line regulation and load regulation are 1.6 and 0.6 mV/mA, respectively.

Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator

Abstract: A digitally-controlled fully integrated voltage regulator (IVR) enables wide autonomous DVFS in a 22 nm graphics execution core. Part of the original power header is converted into a hybrid power stage to support digital low-dropout (DLDO), and switched-capacitor voltage regulator (SCVR) modes, in addition to the original bypass and sleep modes. Using voltage sensing, tunable replica circuit, or a core warning signal, the IVR detects and quickly responds to fast voltage droops to support fast dynamic workload changes without performance degradation. In a prototype, a 3D graphics execution core is powered up by the proposed hybrid IVR demonstrating measured 26% and 82% reduction in core energy in the turbo and the near-threshold voltage (NTV) modes, respectively. The total area overhead of the proposed hybrid IVR is 4% of the core compared to 2% from the original power header. Our digitally assisted control for the droop response shows ${\sim}$ 75% core frequency improvement at 0.84 V.

A Voltage Regulator-Assisted Lightweight AES Implementation Against DPA Attacks

Abstract: In this paper, the mathematical foundations of the security implications of utilizing various on-chip voltage converters as a countermeasure against differential power analysis (DPA) attacks are investigated. An exhaustive mathematical analysis of a recently proposed converter-reshuffling (CoRe) technique is presented where measurement to disclose (MTD) is used to compare the security of the proposed on-chip CoRe regulator with the security of conventional on-chip voltage regulators. A DPA-resistant and lightweight advanced encryption standard (AES) engine implementation that leverages the CoRe technique is proposed. The impact of the centralized and distributed placement of the voltage regulators on the security of a pipelined AES engine is explored. The security implications of the relationship between the clock frequency of the device under attack and the switching frequency of the voltage regulator are investigated. As compared to an unprotected AES engine, the MTD value of the proposed improved pipelined AES engine with a centralized on-chip CoRe regulator is enhanced over 9100 times.

A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads

Abstract: This paper presents an on-chip, low drop-out (LDO) voltage regulator with improved power-supply rejection (PSR) able to drive large capacitive loads. The LDO compensation is achieved via a custom, wide bandwidth capacitance multiplier (c-multiplier) that emulates a nanofarad-range capacitance at the LDO output node. The LDO frequency response resembles that of externally compensated LDOs, leading to a wide PSR frequency range without using an off-chip capacitor. To drive large capacitive loads without stability concerns, the supply-line capacitance of the load circuit is incorporated to the design of the LDO compensation scheme. The power-stability-performance tradeoffs involved in the design are discussed in detail. The LDO and the c-multiplier are implemented in 0.18- $\mu \text{m}$ CMOS technology and target applications with load currents in the 10-mA range. Experimental results show that the LDO achieves a PSR better than −39 dB up to 20 MHz at 1.2 V output voltage, while maintaining a 97.4% current efficiency.