Voltage regulator

About: Voltage regulator is a research topic. Over the lifetime, 33536 publications have been published within this topic receiving 350859 citations.

Design of a robust voltage controller for a buck-boost converter using /spl mu/-synthesis

Abstract: Proposes the structured singular value (/spl mu/) approach to the problem of designing an output voltage regulator for a buck-boost converter with current-mode control. This approach allows a quantitative description of the effects of reactive components' tolerances and operating point variations, which strongly affect the converter dynamics. First, a suitable linear converter model is derived, whose parameter variations are described in terms of perturbations of the linear fractional transformation (LFT) class. Then, /spl mu/-analysis is used to evaluate the robustness of a conventional PI voltage regulator with respect to the modeled perturbations. Finally, the approximate /spl mu/-synthesis procedure known as D-K iteration is used to design a robustly performing regulator. Simulation results are presented, describing the small and large signal behavior of a reduced order approximation of the /spl mu/-synthesized controller.

Comparative study of STATCOM and SVC performance on Dynamic Voltage Collapse of an Electric Power System with Wind Generation

Abstract: One of the major problems of voltage stability is the reactive power limit of the system. Improving the system's reactive power handling capacity via Flexible AC transmission System (FACTS) devices is a solution for prevention of voltage instability. In this paper it is studied the influence of Static Synchronous Compensators (STATCOM) and Static Var Compensators (SVC) in dynamic Voltage Stability during Low Voltage Ride Through (LVRT), in wind farms. The wind turbines are equipped with pitch control coupled with a Fixed Speed Induction Generator (FSIG). Due to the nature of asynchronous operation, system voltage instability of wind farms based on FSIG is largely caused by the excessive reactive power absorption by FSIG after a fault due to the large rotor slip gained during fault. Wind farm models based on FSIG and equipped with either STATCOM or SVC are developed in EUROSTAG. The Automatic Voltage Regulators (AVR) of the generating units and the turbine speed governors were modeled in detail. Different load models were used and the Under Load Tap Changers (ULTC) were also taken into account. Finally, some conclusions that provide a better understanding of the dynamic voltage stability of a system with FSIG model during LVRT, using various capacities of STATCOM and SVC are pointed out.

A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement

Abstract: A low quiescent current asynchronous digital- LDO (D-LDO) regulator integrated with a phase-locked loop (PLL)-modulated switching regulator (SWR) that achieves the near-optimum power management supply for core processor in system-on-chip (SoC). The parallel connection of the asynchronous D-LDO regulator and the ripple-based control SWR can accomplish fast-DVS (F-DVS) operation as well as high power conversion efficiency. The asynchronous D-LDO regulator controlled by bidirectional asynchronous wave pipeline realizes the F-DVS operation, which guarantees high million instructions per second (MIPS) performance of the core processor under distinct tasks. The use of a ripple-based control SWR operating with a leading phase amplifier ensures fast response and stable operation without the need for large equivalent-series-resistance, thus reducing the output voltage ripple for the enhancement of supply quality. The fabricated chip occupies 1.04 mm2 in 40 nm CMOS technology. Experimental results show that a 94% peak efficiency with a voltage tracking speed of 7.5 V/μs as well as the improved MIPS performance by 5.6 times was achieved.

Analysis of the power delivery path from the 12-V VR to the microprocessor

Abstract: This paper offers a thorough analysis of the power delivery path. Based on the power delivery path model, the current slew rate of each loop is derived. The relationship between the inductor current slew rate of the voltage regulator (VR) and the bandwidth is also derived. Then, the level of the voltage spike across the capacitors of each loop is determined, after which the relationship between the bandwidth and the capacitance can be plotted. We find that for today's power delivery structure, the bulk capacitors can be eliminated as long as the bandwidth is pushed beyond 350 kHz. The experimental results of a 2-MHz two-stage 12-V VR verify this analysis.

Boost LED Driver Not Using Output Capacitor and Blocking Diode

Abstract: An LED driver is disclosed that boosts an input voltage to drive any number of LEDs in series. The driver includes a switch-mode current regulator that supplies regulated current pulses to the LEDs. No high voltage output capacitor is used to smooth the current pulses, so the LEDs are turned on any off at the switching frequency. Also, no blocking diode between the switching transistor and the LEDs is used. The cathode of the “bottom” LED in the string is connected to ground via a current sense resistor. In parallel with the sense resistor is connected an RC filter using a small, low voltage filter capacitor. The RC filter provides a substantially smooth feedback voltage for the current regulator to control the duty cycle of the switching transistor so that the feedback voltage matches a reference voltage.