Voltage regulator

About: Voltage regulator is a research topic. Over the lifetime, 33536 publications have been published within this topic receiving 350859 citations.

An experimental large-capacity semiconductor file memory using 16-levels/cell storage

Abstract: A 4-bit semiconductor file memory using 16-levels (4-bits)/cell storage is described. The device has 1-Mb single-transistor dynamic memory cells which are divided into 4-kb sequential-access blocks. It incorporates a staircase-pulse generator for multilevel storage operations, a voltage regulator to protect against power-supply voltage surge, and a soft-error-correction circuit based on a cyclic hexadecimal code. The device is fabricated using 1.3- mu m CMOS technology. It operates with a 5-V single power supply. Random block selection time is 147 mu s, while the sequential data rate is 210 ns. A single-incident alpha particle destroys 4-bit data in two or more adjacent cells. The error correction circuit completely corrects these errors. The soft-error rate under actual operating conditions with error correction is expected to be under 100 FIT (10/sup -7/ h/sup -1/). >

A 13.56 MHz 40 mW CMOS High-Efficiency Inductive Link Power Supply Utilizing On-Chip Delay-Compensated Voltage Doubler Rectifier and Multiple LDOs for Implantable Medical Devices

Abstract: In this paper, a 13.56 MHz CMOS near-field inductive link power supply (ILPS) that can deliver 20 mA output current for implantable medical devices (IMDs) is proposed and fabricated. In the proposed ILPS, the pair of inductive link coils is constructed in the spiral shape with a ferrite core to save space and increase efficiency. Experimental results have shown that the near-field coils can transmit power at the resonant frequency of 13.56 MHz with the transmission efficiency up to 76.3%. The CMOS power regulator is composed of active voltage doubler rectifier (VD) and low-dropout regulators (LDOs). In the active VD with the comparator, the input offset voltage is adjustable for delay compensation and a start-up control circuit is added to achieve robust start-up mechanism. On-chip delay compensation control with SR-latches is proposed to prevent from error glitch switching on offset voltage control and achieve accurate delay compensation so that the reverse current conduction can be avoided and the efficiency can be increased. Three fully-integrated LDOs with rectifier output voltage of 2 V to 1.8 V are realized for analog (ALDO), digital (DLDO), and reference-voltage (RLDO) circuits. Thus the performance of individual LDO can be optimized. The measured output ripple voltage of the active VD is 10.4 mV. The power conversion efficiency (PCE) is 85% under 20 mA output current. The measured dropout voltage is 384 mV. As compared with other designs, the proposed ILPS has lower ripple voltages, lower dropout voltage, and higher PCE.

Switched power supply with current mode regulation

Abstract: A switched mode power supply operating with current mode regulation comprises an output switch coupled to a first winding of a transformer and to a source of input supply voltage. The switch is responsive to a control signal for initiating a pulse width modulated pulse voltage in a second winding of the transformer. A supply circuit coupled to the second winding generates an operating voltage. A feedback signal source monitors both current flowing through the first winding and the operating voltage. A control circuit coupled to the feedback signal source includes an oscillator for generating the control signal at a substantially constant frequency during normal operation and at a variable frequency during abnormal operation. The control circuit is responsive both to the current and to variations of the operating voltage over a regulating range, in a negative feedback loop. The control signal varies the on-time conduction of the output switch in each cycle to stabilize the operating voltage. The oscillator has a frequency control responsive to variations of the operating voltage outside of the regulating range, in a positive feedback loop. The on-time conduction of the output switch is limited to a maximum value by comparing the current to an error signal related to the operating voltage. The error signal varies when the operating voltage is within the regulating range but is limited in magnitude when the operating voltage falls below the regulating range. A DC feedback voltage forms a part of both the negative and positive feedback loops.

Combined control of voltage and frequency of multi-area multisource system incorporating solar thermal power plant using LSA optimised classical controllers

Abstract: This study presents the combined model of automatic load frequency control (ALFC) and automatic voltage regulator (AVR) of a multisource multi-area system for control of voltage, frequency and tie-line power. Each area comprises of a solar thermal, thermal and diesel plant. A more realistic system is studied by considering generation rate constraint and governor dead band (GDB) for the thermal plant. Integral (I)-double derivative (DD) controller with derivative (D) filter (IDDF) is proposed for the combined ALFC and AVR model by considering 1% step load perturbation in area1. The controller parameters are optimised using lightning search algorithm (LSA). The performance of proposed controller is compared with other conventional controllers such as proportional-I (PI), I-D and PI-D. The analysis reveals that the proposed controller outperforms the others in terms of settling time and peak deviations. The comparative performance of various performance indices shows that integral squared error is better than others. Analysis of the effect of GDB with IDDF controller and LSA indicates that the presence of GDB leads to more oscillations in the system dynamics. The sensitivity analysis against the change in magnitude and position of disturbance derived the robustness of the IDDF controller parameters obtained at nominal condition.

Biasing system and method for low voltage DC—DC converters with built-in N-FETs

Abstract: A gate drive supply circuit generating a high-level supply voltage and a low-level supply voltage for driving N-type high-side and low-side power MOSFETs in a multiple-output, low-voltage DC-DC converter integrated circuit. The gate drive supply circuit includes a boost regulator for generating the low-level supply voltage and a charge pump doubler for generating the high-level supply voltage. Both the high-level supply voltage and the low-level supply voltage are distributed to one or more regulators, including but not limited to buck or boost type regulators.