Voltage regulator

About: Voltage regulator is a research topic. Over the lifetime, 33536 publications have been published within this topic receiving 350859 citations.

Modelling and analysis of switching DC-to-DC converters in constant-frequency current-programmed mode

Abstract: An analysis of dc-to-dc switching converters in constant-frequency current-programmed continous conduction mode is performed, and leads to two significant resuslts. The first is that a ramp function, used to eliminate a potential instability, can be chosen uniquely to assure both stability and the fastest possible transient response of the programmed current. The second is the development of an extension of the state-space averaging technique by means of which both the input and output small-signal properties of any such converter may be accurately represented by a linear small-signal equivalent-circuit model. The model is presented and experimentally verified for the cuk converter and for the conventional buck, boost, and buck-boost converters. All models exhibit basically a one-pole control-to-output transfer fuction response.

High-efficiency modulating RF amplifier

Abstract: The present invention, generally speaking, provides for high-efficiency power control of a high-efficiency (e.g., hard-limiting or switch-mode) power amplifier in such a manner as to achieve a desired modulation. In one embodiment, the spread between a maximum frequency of the desired modulation and the operating frequency of a switch-mode DC-DC converter is reduced by following the switch-mode converter with an active linear regulator. The linear regulator is designed so as to control the operating voltage of the power amplifier with sufficient bandwidth to faithfully reproduce the desired amplitude modulation wave-form. The linear regulator is further designed to reject variations on its input voltage even while the output voltage is changed in response to an applied control signal. This rejection will occur even though the variations on the input voltage are of commensurate or even lower frequency than that of the controlled output variation. Amplitude modulation may be achieved by directly or effectively varying the operating voltage on the power amplifier while simultaneously achieving high efficiency in the conversion of primary DC power to the amplitude modulated output signal. High efficiency is enhanced by allowing the switch-mode DC-to-DC converter to also vary its output voltage such that the voltage drop across the linear regulator is kept at a low and relatively constant level. Time-division multiple access (TDMA) bursting capability may be combined with efficient amplitude modulation, with control of these functions being combined. In addition, the variation of average output power level in accordance with commands from a communications system may also be combined within the same structure.

Modeling of VSC Connected to Weak Grid for Stability Analysis of DC-Link Voltage Control

Abstract: In this paper, a small-signal model of voltage source converter (VSC) is developed to investigate the stability of dc-link voltage control. This model contributes to representing the dc-link voltage dynamics characteristics of VSC integrated to weak grid. Effects of grid strength, operating point, and control loops’ interactions on the performance of VSC are taken into consideration. Based on the proposed small-signal model, eigenvalue analysis is employed to study the stability of dc-link voltage control with varying operating conditions. Analysis results show that control loops’ interactions introduce a partial positive feedback to the dc-link voltage control in weak grid. Furthermore, the effect of control loops’ interactions on dc-link voltage control stability reaches largest when the bandwidth of the phase-locked loop is close to that of the dc-link voltage control. Time-domain simulations and experiments were conducted to validate the analysis.

An Output-Capacitorless Low-Dropout Regulator With Direct Voltage-Spike Detection

Abstract: An output-capacitorless low-dropout regulator (LDO) with a direct voltage-spike detection circuit is presented in this paper. The proposed voltage-spike detection is based on capacitive coupling. The detection circuit makes use of the rapid transient voltage at the LDO output to increase the bias current momentarily. Hence, the transient response of the LDO is significantly enhanced due to the improvement of the slew rate at the gate of the power transistor. The proposed voltage-spike detection circuit is applied to an output-capacitorless LDO implemented in a standard 0.35-?m CMOS technology (where VTHN ? 0.5 V and VTHP ? -0.65 V). Experimental results show that the LDO consumes 19 ?A only. It regulates the output at 0.8 V from a 1-V supply, with dropout voltage of 200 mV at the maximum output current of 66.7 mA. The voltage spike and the recovery time of the LDO with the proposed voltage-spike detection circuit are reduced to about 70 mV and 3 ?s, respectively, whereas they are more than 420 mV and 30 ?s for the LDO without the proposed detection circuit.

A 6- $\mu$ W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology

Abstract: An output-capacitorless low-dropout regulator (LDO) compensated by a single Miller capacitor is implemented in a commercial 90-nm CMOS technology. The proposed LDO makes use of the small transistors realized in nano-scale technology to achieve high stability, fast transient performance and small voltage spikes under rapid load-current changes without the need of an off-chip capacitor connected at the LDO output. Experimental result verifies that the proposed LDO is stable for a capacitive load from 0 to 50 pF (estimated equivalent parasitic capacitance from load circuits) and with load capability of 100 mA. Moreover, the gain-enhanced structure provides sufficient loop gain to improve line regulation to 3.78 mV/V and load regulation to 0.1 mV/mA, respectively. The embedded voltage-spike detection circuit enables pseudo Class-AB operation to drive the embedded power transistor promptly. The measured power consumption is only 6 μW under a 0.75-V supply. The maximum overshoot and undershoot under a 1.2-V supply are less than 66 mV for full load current changes within 100-ns edge time, and the recovery time is less than 5 μs.