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Voltage regulator

About: Voltage regulator is a research topic. Over the lifetime, 33536 publications have been published within this topic receiving 350859 citations.


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Journal ArticleDOI
TL;DR: In this paper, a simple and accurate analytical switching loss model is proposed for synchronous buck voltage regulators (VRs), which includes the impact of common source inductance and switch parasitic inductances on switching loss.
Abstract: In this paper, a review of switching loss mechanisms for synchronous buck voltage regulators (VRs) is presented. Following the review, a new simple and accurate analytical switching loss model is proposed for synchronous buck VRs. The model includes the impact of common source inductance and switch parasitic inductances on switching loss. The proposed model uses simple equations to calculate the rise and fall times and piecewise linear approximations of the high-side MOSFET voltage and current waveforms to allow quick and accurate calculation of switching loss in a synchronous buck VR. A simulation program with integrated circuit emphasis (Spice) simulations are used to demonstrate the accuracy of the voltage source driver model operating in a 1-MHz synchronous buck VR at 12-V input, 1.3-V output. Switching loss was estimated with the proposed model and compared to Spice measurements. Experimental results are presented to demonstrate the accuracy of the proposed model.

139 citations

Journal ArticleDOI
TL;DR: A computer program which predicts the DC and transient performance of monolithic integrated circuits in the presence of electrothermal interactions on the integrated circuit die is described and thermal modeling of the die/package structure and the numerical analysis procedure is discussed.
Abstract: A computer program which predicts the DC and transient performance of monolithic integrated circuits in the presence of electrothermal interactions on the integrated circuit die is described. The thermal modeling of the die/package structure and the numerical analysis procedure is discussed. Experimental and simulation results are compared for monolithic operational amplifiers, voltage regulators, and a temperature-stabilized voltage reference.

139 citations

Journal ArticleDOI
07 Feb 2000
TL;DR: In this paper, a low-power high-speed CMOS signaling interface that operates off of an adaptively regulated supply is presented, where a feedback loop adjusts the supply voltage on a chain of inverters until the delay through the chain is equal to half of the input period.
Abstract: This paper presents a low-power high-speed CMOS signaling interface that operates off of an adaptively regulated supply. A feedback loop adjusts the supply voltage on a chain of inverters until the delay through the chain is equal to half of the input period. This voltage is then distributed to the I/O subsystem through an efficient switching power-supply regulator. Dynamically scaling the supply with respect to frequency leads to a simple and robust design consisting mostly of digital CMOS gates, while enabling maximum energy efficiency. The interface utilizes high-impedance drivers for operation across a wide range of voltages and frequencies, a dual-loop delay-locked loop for accurate timing recovery, and an input receiver whose bandwidth tracks with the I/O frequency to filter out high-frequency noise. Test chips fabricated in a 0.35-/spl mu/m CMOS technology achieve transfer rates of 0.2-1.0 Gb/s/pin with a regulated supply ranging from 1.3-3.2 V.

139 citations

Patent
15 May 2001
TL;DR: In this paper, the authors proposed a voltage regulator in which a switching circuit intermittently couples the input terminal and the output terminal in response to a digital control signal, and a voltage sensor generates a digital second feedback signal derived from the output voltage.
Abstract: A digitally implemented voltage regulator in which a switching circuit intermittently couples the input terminal and the output terminal in response to a digital control signal. A current sensor generates a digital first feedback signal derived from the current passing through the switching circuit, and a voltage sensor generates a digital second feedback signal derived from the output voltage. A digital controller receives and uses the digital feedback signals to generate the digital control signal.

138 citations

Journal ArticleDOI
TL;DR: A fully integrated battery powered RFID integrated circuit (IC) for operation at ultrahigh frequency (UHF) and microwave bands and can also work as a passive RFID tag without a battery or when the battery has died, allays one of the major drawbacks of currently available active tags.
Abstract: We present for the first time, a fully integrated battery powered RFID integrated circuit (IC) for operation at ultrahigh frequency (UHF) and microwave bands The battery powered RFID IC can also work as a passive RFID tag without a battery or when the battery has died (ie, voltage has dropped below 13 V); this novel dual passive and battery operation allays one of the major drawbacks of currently available active tags, namely that the tag cannot be used once the battery has died When powered by a battery, the current consumption is 700 nA at 15 V (400 nA if internal signals are not brought out on test pads) This ultra-low-power consumption permits the use of a very small capacity battery of 100 mA-hr for lifetimes exceeding ten years; as a result a battery tag that is very close to a passive tag both in form factor and cost is made possible The chip is built on a 1-mum digital CMOS process with dual poly layers, EEPROM and Schottky diodes The RF threshold power at 245 GHz is -19 dBm which is the lowest ever reported threshold power for RFID tags and has a range exceeding 35 m under FCC unlicensed operation at the 24-GHz microwave band The low threshold is achieved with architectural choices and low-power circuit design techniques At 915 MHz, based on the experimentally measured tag impedance (92-j837) and the threshold spec of the tag (200 mV), the theoretical minimum range is 24 m The tag initially is in a "low-power" mode to conserve power and when issued the appropriate command, it operates in "full-power" mode The chip has on-chip voltage regulators, clock and data recovery circuits, EEPROM and a digital state machine that implements the ISO 18000-4 B protocol in the "full-power" mode We provide detailed explanation of the clock recovery circuits and the implementation of the binary sort algorithm, which includes a pseudorandom number generator Other than the antenna board and a battery, no external components are used

138 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202382
2022212
2021320
2020699
2019947
2018973