Voltage regulator

About: Voltage regulator is a research topic. Over the lifetime, 33536 publications have been published within this topic receiving 350859 citations.

Step-up switching-mode converter with high voltage gain using a switched-capacitor circuit

Abstract: A new circuit is proposed for a steep step-up of the line voltage. It integrates a switched-capacitor (SC) circuit within a boost converter. An SC circuit can achieve any voltage ratio, allowing for a boost of the input voltage to high values. It is unregulated to allow for a very high efficiency. The boost stage has a regulation purpose. It can operate at a relatively low duty cycle, thus avoiding diode-reverse recovery problems. The new circuit is not a cascade interconnection of the two power stages; their operation is integrated. The simplicity and robustness of the solution, the possibility of getting higher voltage ratios than cascading boost converters, without using transformers with all their problems, and the good overall efficiency are the benefits of the proposed converter.

Architecture and IC implementation of a digital VRM controller

Abstract: This paper develops the architecture of a digital PWM controller for application in multiphase voltage regulation modules (VRMs). In this context, passive current sharing and VRM transient response with nonzero controller delay are analyzed. A scheme for sensing a combination of the VRM output voltage and output current with a single low-resolution window analog-to-digital converter (ADC) is proposed. The architecture and IC implementation of a digital PWM (DPWM) generation module, using a ring-oscillator-multiplexer scheme, is discussed. Experimental results from a prototype VRM and a partial controller IC implementation are presented.

Optimal Distribution Voltage Control and Coordination With Distributed Generation

Abstract: In recent years, distributed generation, as clean natural energy generation and cogeneration system of high thermal efficiency, has increased due to the problems of global warming and exhaustion of fossil fuels. Many of the distributed generations are set up in the vicinity of the customer, with the advantage that this decreases transmission losses. However, output power generated from natural energy, such as wind power, photovoltaics, etc., which is distributed generation, is influenced by meteorological conditions. Therefore, when the distributed generation increases by conventional control techniques, it is expected that the voltage change of each node becomes a problem. Proposed in this paper is the optimal control of distribution voltage with coordination of distributed installations, such as the load ratio control transformer, step voltage regulator (SVR), shunt capacitor, shunt reactor, and static var compensator. In this research, SVR is assumed to be a model with tap changing where the signal is received from a central control unit. Moreover, the communication infrastructure in the supply of a distribution system is assumed to be widespread. The genetic algorithm is used to determine the operation of this control. In order to confirm the validity of the proposed method, simulations are carried out for a distribution network model with distributed generation (photovoltaic generation).

A Method for Placement of DG Units in Distribution Networks

Abstract: In this paper, a method for placement of distributed generation (DG) units in distribution networks has been presented. This method is based on the analysis of power flow continuation and determination of most sensitive buses to voltage collapse. This method is executed on a typical 34-bus test system and yields efficiency in improvement of voltage profile and reduction of power losses; it also may permit an increase in power transfer capacity, maximum loading, and voltage stability margin.

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

Abstract: This paper describes a multi-core processor that integrates 48 cores, 4 DDR3 memory channels, and a voltage regulator controller in a 64 2D-mesh network-on-chip architecture. Located at each mesh node is a five-port virtual cut-through packet-switched router shared between two IA-32 cores. Core-to-core communication uses message passing while exploiting 384 KB of on-die shared memory. Fine grain power management takes advantage of 8 voltage and 28 frequency islands to allow independent DVFS of cores and mesh. At the nominal 1.1 V supply, the cores operate at 1 GHz while the 2D-mesh operates at 2 GHz. As performance and voltage scales, the processor dissipates between 25 W and 125 W. The processor is implemented in 45 nm Hi-K CMOS and has 1.3 billion transistors.