Voltage regulator

About: Voltage regulator is a research topic. Over the lifetime, 33536 publications have been published within this topic receiving 350859 citations.

Adaptive compensating ramp generator for current-mode DC/DC converters

Abstract: A circuit (20, 40, 50, 60) for generating an optimal compensating ramp voltage signal V cramp , with the minimum necessary slope, m c for a current mode DC/DC converter is shown The adaptive compensating ramp generating circuit (20) is comprised of two voltage dividers (22, 24), the first voltage divider 22 divides an input voltage V IN and the second voltage divider 24 divides an output voltage V OUT The first voltage divider (22) has two resistors (26, 28) in series: the first resistor (26) has a resistance of (1/B-1) * R ohms and the second resistor (28) has a resistance of R ohms V OUT is divided by the second voltage divider (24) having two resistors (29, 30) in series: the first resistor (29) has a resistance of (1/A-1) * R ohms and the second resistor (30) has a resistance of R ohms The constants A, B, and C are selected for the particular type of DC/DC converter employed The divided voltages A * V OUT and B * V IN are input into a voltage controlled current source (32) The voltage controlled current source (32) has a scaling resistor R scale , an amplifier (36), a transistor Q, and a diode D1 The output of the current source (38) is coupled to a capacitor C ramp whose voltage realizes the slope of the compensating ramp signal, V cramp The capacitor C ramp is charged through R scale

Linear voltage regulator with zero mobile compensation

Abstract: A method and apparatus to dynamically modify the internal compensation of a low drop out linear voltage regulator is presented. The process involves using zero mobile compensation; when the output pole of the voltage regulator moves, a compensating zero is moved toward higher frequencies. This compensation zero is used to compensate the effect of a second pole in the loop gain. The circuit includes an input stage having an error amplifier. The error amplifier includes a differential stage output coupled to an output terminal of the buffer stage. An output stage of the circuit includes an output transistor having a conduction terminal connected to an output terminal of the voltage regulator, and having a control terminal coupled to the output terminal of the buffer stage. Additionally, a variable compensation network is connected between the differential stage output and a voltage reference. This variable compensation network can include an RC circuit having a resistive transistor. The resistance value of the resistive transistor is modulated according to the output load current of the voltage regulator, thereby changing the location of the compensating zero.

Design and Implementation of a Fast Dynamic Control Scheme for Capacitor-Supported Dynamic Voltage Restorers

Abstract: This paper presents a fast dynamic control scheme for capacitor-supported single-phase dynamic voltage restorers (DVRs) for inductive loads. The scheme consists of two main control loops as inner and outer loops. The inner loop is used to dictate the gate signals for the switches in the DVR. It is based on the boundary control method with the second-order switching surface. The load voltage can ideally be reverted to the steady state in two switching actions during a supply voltage dip. The outer loop is used to generate the DVR output reference for the inner loop. It has three control modes for achieving two different functions, including the output regulation and output restoration. The first mode is for regulating the capacitor voltage on the dc side of the inverter, so that the output of the DVR is regulated at the nominal voltage. The second mode is for restoring the output with the near minimum energy injection by the DVR during a voltage dip. The third mode is in maximum voltage injection and will be activated when the capacitor voltage is reduced to a level that starts distorting the output voltage in the second mode. The mode boundaries will be derived in this paper. By studying the small-signal characteristics of the control loops, a set of design procedures will be derived. A 500 VA, 110 V, 60 Hz prototype has been built and tested with nonlinear inductive loads. The dynamic behaviors of the prototype under different voltage dip depths will be investigated.

Method and apparatus for configuration of processor operating parameters

Abstract: A configuration system including a processor having memory for storing operating parameters and configuration logic for retrieving the operating parameters and configuring a computer system to achieve a desired performance level. The configuration logic preferably includes programmable regulators, such as a voltage regulator and a clock synthesizer, for asserting an operating voltage and clock signal, respectively, to the processor. These operating signals are asserted at nominal levels at start up to allow the processor to operate at a reduced, yet adequate performance level. The stored operating parameters are asserted onto a processor data bus by the processor during start up and stored in corresponding data latches. The parameters are further provided to the programmable regulators, such as a voltage regulator, a clock synthesizer, for example, which convert the operating signals from the nominal levels to optimal levels corresponding to the retrieved parameters. The operating signals may further be dynamically reconfigured by storing new parameters in the data latches, if desired. Thus, the regulators may be dynamically reconfigured during operation to achieve operating criterion, such as slowing down the clock frequency during a low power mode.

Reverse Nested Miller Compensation Using Current Buffers in a Three-Stage LDO

Abstract: A novel frequency compensation scheme called reverse nested Miller compensation using current buffers (RNMCCB) for three-stage amplifiers is proposed. As opposed to previous reverse nested schemes, our work uses inverting gain stages for both the second and third stages. The outer compensation loop utilizes a current mirror as an inverting current buffer (CB), and the inner loop uses a common-gate amplifier as a CB, creating two left-half-plane (LHP) zeros. We introduce a simple and effective method of placing a resistor in series with a CB for accurate placement of LHP zeros. As a design example of the RNMCCB scheme, we propose a three-stage low dropout voltage regulator (LDO) in a 0.5-?m CMOS process to supply 1.21 V to a load ranging from 1 ?A to 100 mA. Our design goals were to simultaneously achieve very high current efficiency and very low transient output voltage variation. As such, we achieved a 99.95% current efficiency and a maximum load transient output voltage variation of ±48 mV with an output capacitor of 100 nF. Experimental results, in good agreement with theoretical analysis, validate the novel RNMCCB frequency compensation scheme.