Wafer

About: Wafer is a research topic. Over the lifetime, 118092 publications have been published within this topic receiving 1139849 citations.

Silicon quantum wire array fabrication by electrochemical and chemical dissolution of wafers

Abstract: Indirect evidence is presented that free‐standing Si quantum wires can be fabricated without the use of epitaxial deposition or lithography. The novel approach uses electrochemical and chemical dissolution steps to define networks of isolated wires out of bulk wafers. Mesoporous Si layers of high porosity exhibit visible (red) photoluminescence at room temperature, observable with the naked eye under <1 mW unfocused (<0.1 W cm−2) green or blue laser line excitation. This is attributed to dramatic two‐dimensional quantum size effects which can produce emission far above the band gap of bulk crystalline Si.

100-GHz Transistors from Wafer-Scale Epitaxial Graphene

Abstract: The high carrier mobility of graphene has been exploited in field-effect transistors that operate at high frequencies. Transistors were fabricated on epitaxial graphene synthesized on the silicon face of a silicon carbide wafer, achieving a cutoff frequency of 100 gigahertz for a gate length of 240 nanometers. The high-frequency performance of these epitaxial graphene transistors exceeds that of state-of-the-art silicon transistors of the same gate length.

Block copolymer lithography: Periodic arrays of ~1011 holes in 1 square centimeter

Abstract: Dense periodic arrays of holes and dots have been fabricated in a silicon nitride–coated silicon wafer. The holes are 20 nanometers across, 40 nanometers apart, and hexagonally ordered with a polygrain structure that has an average grain size of 10 by 10. Spin-coated diblock copolymer thin films with well-ordered spherical or cylindrical microdomains were used as the templates. The microdomain patterns were transferred directly to the underlying silicon nitride layer by two complementary techniques that resulted in opposite tones of the patterns. This process opens a route for nanometer-scale surface patterning by means of spontaneous self-assembly in synthetic materials on length scales that are difficult to obtain by standard semiconductor lithography techniques.

Low-temperature wafer-scale production of ZnO nanowire arrays.

Abstract: Since the first report of ultraviolet lasing from ZnO nanowires, substantial effort has been devoted to the development of synthetic methodologies for one-dimensional ZnO nanostructures. Among the various techniques described in the literature, evaporation and condensation processes are favored for their simplicity and high-quality products, but these gas-phase approaches generally require economically prohibitive temperatures of 800–900 8C. Despite recent MOCVD schemes that reduced the deposition temperature to 450 8C by using organometallic zinc precursors, the commercial potential of gas-phase-grown ZnO nanowires remains constrained by the expensive and/or insulating (for example, Al2O3) substrates required for oriented growth, as well as the size and cost of the vapor deposition systems. A low-temperature, large-scale, and versatile synthetic process is needed before ZnO nanowire arrays find realistic applications in solar energy conversion, light emission, and other promising areas. Solution approaches to ZnO nanowires are appealing because of their low growth temperatures and good potential for scale-up. In this regard, Vayssieres et al. developed a hydrothermal process for producing arrays of ZnO microrods and nanorods on conducting glass substrates at 95 8C. Recently, a seeded growth process was used to make helical ZnO rods and columns at a similar temperature. Here we expand on these synthetic methods to produce homogeneous and dense arrays of ZnO nanowires that can be grown on arbitrary substrates under mild aqueous conditions. We present data for arrays on four-inch (ca. 10 cm) silicon wafers and two-inch plastic substrates, which demonstrate the ease of commercial scale-up. The simple two-step procedure yields oriented nanowire films with the largest surface area yet reported for nanowire arrays. The growth process ensures that a majority of the nanowires in the array are in direct contact with the substrate and provide a continuous pathway for carrier transport, an important feature for future electronic devices based on these materials. Well-aligned ZnO nanowire arrays were grown using a simple two-step process. In the first step, ZnO nanocrystals (5–10 nm in diameter) were spin-cast several times onto a four-inch Si(100) wafer to form a 50–200-nm thick film of crystal seeds. Between coatings, the wafer was annealed at 150 8C to ensure particle adhesion to the wafer surface. The ZnO nanocrystals were prepared according to the method of Pacholski. A NaOH solution in methanol (0.03m) was added slowly to a solution of zinc acetate dihydrate (0.01m) in methanol at 60 8C and stirred for two hours. The resulting nanoparticles are spherical and stable for at least two weeks in solution. After uniformly coating the silicon wafer with ZnO nanocrystals, hydrothermal ZnO growth was carried out by suspending the wafer upside-down in an open crystallizing dish filled with an aqueous solution of zinc nitrate hydrate (0.025m) and methenamine or diethylenetriamine (0.025m) at 90 8C. Reaction times spanned from 0.5 to 6 h. The wafer was then removed from solution, rinsed with deionized water, and dried. A field-emission scanning electron microscope (FESEM) was used to examine the morphology of the nanowire array across the entire wafer, while single nanowires were characterized by transmission electron microscopy (TEM). Nanowire crystallinity and growth direction were analyzed by X-ray diffraction and electron diffraction techniques. SEM images taken of several four-inch samples showed that the entire wafer was coated with a highly uniform and densely packed array of ZnO nanowires (Figure 1). X-ray diffraction (not shown) gave a wurtzite ZnO pattern with an enhanced (002) peak resulting from the vertical orientation of the nanowires. A typical synthesis (1.5 h) yielded wires with diameters ranging between 40–80 nm and lengths of 1.5–2 mm.

The Evolution of Silicon Wafer Cleaning Technology

Abstract: The purity of wafer surfaces is an essential requisite for the successful fabrication of VLSI and ULSI silicon circuits. Wafer cleaning chemistry has remained essentially unchanged in the past 25 years and is based on hot alkaline and acidic hydrogen peroxide solutions, a process known as "RCA Standard Clean." This is still the primary method used in the industry. What has changed is its implementation with optimized equipment: from simple immersion to centrifugal spraying, megasonic techniques, and enclosed system processing that allow simultaneous removal of both contaminant films and particles. Improvements in wafer drying by use of isopropanol vapor or by "slow‐pull" out of hot deionized water are being investigated. Several alternative cleaning methods are also being tested, including choline solutions, chemical vapor etching, and UV/ozone treatments. The evolution of silicon wafer cleaning processes and technology is traced and reviewed from the 1950s to August 1989.