Showing papers on "Wafer published in 1969"

Hourglass-shaped conductive connection through semiconductor structures

Abstract: An integrated semiconductor structure including the fabrication thereof, and more particularly, an improved means for interconnecting the two planar surfaces of a semiconductor wafer. To provide the electrically conductive interconnections through the wafer, a hole is etched, insulated, and metallized. Active or passive devices may be formed on either or both sides of the wafer and connected to a substrate by solder pads without the use of beam leads or flying lead bonding.

Temperature Distribution and Stresses in Circular Wafers in a Row During Radiative Cooling

Abstract: A model is proposed in which transient temperature profiles in circular wafers in a row during cooling are analyzed. Various effects such as the number of wafers in a row, the position of the wafer in a row, the ratio of the wafer radius to the wafer spacing, multiple reflections, and the contribution of conduction are considered. It is shown that drastic radial variations of temperature can occur because of the geometrical factor affecting the efficiency of radiative transfer in various parts of a wafer. Thermal stresses thus induced in the cooling wafer can often exceed the yield stress in silicon wafers, causing plastic deformation. The phenomenon of ``thermal warping'' is briefly discussed.

Gas plasma vapor etching process

Abstract: Gas plasma vapor etching process utilized for removing portions of material from a semiconductor structure for a number of purposes including polishing and cleaning of the silicon wafers, finding pin holes in an insulating layer covering the semiconductor wafer and forming scribe lines in the wafer to thereafter permit the wafer to be mechanically broken into dice without any substantial damage to the dice

Radiation resistance of Al 2 O 3 MOS devices

Abstract: Integrated circuits employing MOS devices will play a vital role in tomorrow's civilian and military electronics if their degradation in a radiation environment can be eliminated. One possible approach toward alleviating radiation effects in MOS devices is to use a material with a defect structure that does not allow predominant trapping of either holes or electrons as a gate insulator. This has been done by constructing MOS devices with plasma-grown aluminum oxide. The Al 2 O 3 films are formed by first depositing aluminum on freshly cleaned and properly prepared silicon wafers. Subsequently this aluminum is oxidized in an oxygen plasma and device fabrication is then completed. The devices have excellent characteristics and stability, and their fabrication is not restricted by the conditions of the ultra-clean procedures necessary for SiO 2 -Si devices. Exposure to 1-MeV electron bombardment at various fluence levels and bombardment-bias conditions shows that these structures possess remarkable radiation resistance. Up to a fluence of 1 × 1013e/cm2, under positive or negative bias, no oxide charge buildup or interface state generation is detectable. Above that fluence, only small shifts are observed. This indicates that an order of magnitude improvement in device hardening can be achieved by the use of this material.

Growth and Characterization of Spinel Single Crystals for Substrate Use in Integrated Electronics

Abstract: An extensive study has been made on the growth and characterization of single‐crystal magnesium aluminate spinel. This material has received attention as a superior substrate for epitaxial silicon‐integrated electronic devices. Large spinel single crystals within the compositional range MgO:Al2O3–MgO:3Al2O3, have been successfully grown by flame fusion using a modern three‐tube post‐mix‐type Verneuil burner. Substrate wafers of (111), (100), and (110) orientations were prepared for silicon epitaxy. Surface preparation of the substrates was studied, including mechanical polishing, hydrogen annealing, and chemical etching. The composition, lattice parameter, crystalline perfection, mechanical hardness, thermal stability, and dielectric properties of the spinel single crystals have been characterized by various techniques in an effort to obtain a basic understanding for substrate use of this material system. Some trends in the dependence of these properties on composition were observed. In particular, the th...

Discretionary interconnection process

Abstract: A process wherein numerous identical or similar cells are formed into a continuous chain of such cells on a single semiconductor wafer is shown. The cells are cataloged as either good or bad cells and then a layer of dielectric followed by a pattern of conductors is deposited over all of the cells. Connections are discretionarily made to the good cells by omitting to etch holes through the dielectric layer over the contacts of bad cells and by shorting across all cells and then removing the shorts across the good cells.

Method for epitactic precipitation of silicon at low temperatures

Abstract: A method for producing highly pure, monocrystalline silicon layers, with or without dopant additions, upon a wafer shaped substrate body, which comprises thermal dissociating a gaseous silane compound, and by precipitating silicon upon a heated substrate body located in a reaction chamber. The crystalline structure of the silicon body is exposed e.g. by etching and its surface is flooded by the reaction gas. The silane compound is a dihalogen silane of formula SiH2X2, wherein X is chlorine, bromine, or iodine. The thermal dissociation is effected by heating the substrate body at low temperatures, preferably within a temperature range between 600* and 1,000* C.

An electron imaging system for the fabrication of integrated circuits

Abstract: An ultrahigh resolution electron image projection tube has been investigated as a means for fabricating large arrays of micron size transistors. Electrons are derived from an air stable photocathode whose surface contains an image of the desired array of diffusion or contact windows. Coaxial electromagnetic fields focus the electron image onto the silicon wafer targets. The observed resolution (∼ 1 μ), useful area (∼ 1 in. dia.), and depth of focus (∼ 25 μ) exceed that of any known light optics fabrication system. Also, the image tube approach is more efficient than the use of a single scanned beam, since large arrays can be exposed in a single operation. A method has been demonstrated for performing alignments.

Retaining trays for semiconductor wafers and the like

Abstract: A series of marginally registrable plastic trays having a plurality of wells for accommodating semiconductor wafers and similar elements The retaining wells are provided with a wall having a surface configuration such that the critical surface of the wafer does not contact the well A removable cap is disposed over each of the retaining wells and is provided with means for engaging the upwardly presented surface of the semiconductor wafer Each of the trays is registrable with like trays so that a series of these trays can be stacked, wrapped, and shipped as a unit

Assemblies of semiconductor devices having mounting pillars as circuit connections

Abstract: Mounting pillars comprising electrical connections between device contact pads on a semiconductor wafer and conductors, the conductors possibly being on a substrate member, are formed by initially forming protrusions on the substrate member, if provided, or the semiconductor wafer and depositing conductive material over the protrusions to provide respectively conductors or device contact pads having integral mounting pillars.

Camera tube having a semiconductor target with pn mosaic regions covered by a continuous perforated conductive layer

Abstract: A camera tube employing a radiation-sensitive target positioned to be scanned by an electron beam. The target comprises a wafer of semiconductive material having a substrate of semi-conductor material of one conductivity type, e.g. n-type silicon. A plurality of islands separated by grooves project from the substrate on the side scanned by the electron beam. These islands are of opposite conductivity type and form with the substrate rectifying junctions. On the exposed surface of each island is a metal layer which is separated from the semiconductive material of the island by an insulating layer having an aperture therein.

Method of grooving semiconductor wafer for the dividing thereof

Abstract: The method of uniformly shaving identical side walls of V grooves in silicon wafers by subjecting such wafer to the diverging cutting edges of one triangular facet of a diamond cutting head with such facet set at an acute angle relative to the surface of the wafer and the apex of such facet in a trailing disposition at the desired depth of groove to be made such that the diverging cutting edges divert silicon shavings toward center of the groove and the trailing apex scrapes the shavings out of the groove in the direction of movement of the cutting head preparatory to the breaking of such V grooved wafers into independent dies by supporting such wafer grooved face down on a pad under a plastic cover stretched tightly thereover and while subjecting the wafer to the rolling action of a roller of a diameter determined by the distance between the V grooves formed on such wafer.

System and method for positioning a wafer coated with photoresist and for controlling the displacements of said wafer in a scanning electron apparatus

Abstract: System and method for positioning a wafer coated with photoresist and for controlling the displacements of this wafer in a scanning electron beam apparatus such as a scanning electron microscope. In this system, the sample holder of the scanning electron microscope comprises, in addition to the conventional micrometer mechanisms, three piezoelectric actuators as fine adjustment means for positioning the wafer in two orthogonal directions and in rotation. The sample holder is further coupled to three interferometers which are located within the evacuated enclosure of the microscope and are monitored by a set of fringe counting units located outside the enclosure. The provision of a programmer and of a servocontrol system allow the displacements of the wafer to be automatically controlled and measured.

Apparatus including a wire tipped probe for testing semiconductor wafers

Abstract: An apparatus for sequentially testing devices on a semiconductor wafer comprising a support column including means for receipt of a removable platform on which a wafer to be tested is mounted. A plurality of probes are disposed about the support column. The probes have a bird-beaklike shape and are thin in comparison to their width, whereby a large number of probes can be disposed in circular array around the support column.

Method of producing thin layer components with at least one insulating intermediate layer

Abstract: Described is a method of producing thin layer components, separated by at least one insulating layer and comprised of semiconductor material, particularly silicon. The method is characterized by the fact that an amorphous layer of insulated material is pyrolytically precipitated on a substrate wafer, comprised of monocrystalline semiconductor material. The amorphous layer is converted into a monocrystalline layer by using the monocrystalline substrate and the thus formed substrate, which has a homogeneous crystallographic orientation, is used to grow another epitactic semiconductor layer, preferably of silicon.

Wafer polishing apparatus and method

Abstract: A WAFER TO BE POLISHED IS MOUNTED ON ONE END OF A MOUNTING CYLINDER. AN ANNULAR FLANGE THREADED TO THE MOUNTING CYLINDER IS ADJUSTED SUCH THAT THE EXPOSED WAFER SURFACE PROTRUDES BEYOND A BRAKE SURFACE OF THE FLANGE BY A DISTANCE EQUAL TO THE THICKNESS OF THE WAFER MATERIAL TO BE REMOVED. A STABILIZING MEMBER SLIDEABLY, FITS OVER THE FLANGE TO FORM WITH THE OTHER COMPONENTS A POLISHING ASSEMBLY THAT IS THEN PLACED, WAFER SURFACE DOWN, IN A POLISHING PAN. THE PAN IS AGITATED SUCH THAT THE ASSEMBLY DESCRIBES A RANDOM MOTION UNTIL THE WAFER HAS BEEN POLISHED TO ITS DESIRED THICKNESS, AT WHICH TIME THE BRAKE SURFACE CONTACTS THE POLISHING SURFACE OF THE PAN AND TERMINATES MOVEMENT OF THE ASSEMBLY RELATIVE TO THE PAN.

Process for wafer fabrication of high blocking voltage silicon elements

Abstract: A silicon wafer provided with at least one voltage-blocking junction is strengthened by epitaxially depositing silicon onto one major surface. The wafer is then etched to form grooved surfaces intersecting the junction. A passivation layer is deposited and fast diffusing impurities are gettered and removed. The wafer is broken into a plurality of discrete, separately useable silicon elements.

Dielectric isolated integrated circuit substrate processes

Abstract: Dielectric isolation has proven effective in raising inter-device breakdown voltages, lowering parasitic capacitances, and increasing resistance to radiation damage. The fabrication of a dielectric-isolated substrate, prior to diffusions, requires adequate control of the thickness of the epitaxial layer, of crowning and warpage, and of a necessarily smooth, damage-free surface. The mere juxtaposition of three or more layers of different materials, even before diffusion-induced strains, creates special problems because of coefficient-of-expansion mismatches. In addition, the substrates must pass through subsequent diffusion cycles and permit the fabrication of transistors with characteristics as good as (or better than) those made on p-n junction isolated substrates. There are three major methods of using silicon dioxide as a dielectric to separate active areas of an integrated circuit: 1) shape-back to the channels of a wafer which has had channels etched out and filled with polycrystalline silicon; 2) etch out and fill in with single crystal on an n+wafer which has already had isolation moats created; and 3) growth of polycrystalline silicon prior to etching the isolating channels. This paper describes and compares these methods.

Monolithic electric wave filters

Abstract: A crystal wafer supports two or more pairs of opposing electrodes to form a monolithic crystal filter. The wafer material has a high piezoelectric coupling coefficient. Inharmonic oscillations are suppressed by plating the electrodes on the surfaces of recesses in the faces of the wafer.

Method of producing air-isolated integrated circuits

Abstract: Islands of dielectrically isolated monocrystalline silicon, fabricated in a polycrystalline base, are first produced. Device fabrication and beam lead interconnection follow. Thereafter the planar top surface is covered with an etch-resistant wax and the polycrystalline base is removed by etching. In another embodiment, SiO2 is grown on a grooved, monocrystalline silicon slice, and polycrystalline silicon is deposited thereover. The slice is then lapped down on the top side so that the polycrystalline silicon and SiO2 form barriers. Second side is lapped after devices are fabricated and after beam leads are formed. Active devices and beam leads are fabricated on one surface, and the polycrystalline material is lapped and etched away from the back. In either case, the remaining structure is an air-isolated beam lead device.

Ohmic contact system

Abstract: An ohmic contact system for a ceramic body having a predetermined relationship between various physical characteristics, such as temperature and resistance, for example, a wafer of semiconducting barium titanate having a positive temperature coefficient of resistance. A film of germanium is deposited on at least one surface of the wafer to protect the surface properties thereof. A layer of a preselected metal which adheres well to germanium and is readily bondable, such as gold, is deposited on the germanium film. A layer of a preselected barrier layer, such as nickel, which functions to prevent the penetration of subsequently applied process materials, such as solder, which might adversely affect the underlying gold layer, is deposited on the gold layer. An exterior layer of a readily solderable material which adheres well to the underlying nickel layer, such as gold, is deposited on the nickel layer. An external electrical conductor may then be readily soldered to the external gold layer to provide a good ohmic and mechanical contact to the wafer. An additional base layer of a preselected material, such as palladium, which adheres well to nickel and to gold may be deposited intermediate the nickel layer and the exterior gold layer to provide an improved base for the external gold layer.

Method for forming epitaxial crystals or wafers in selected regions of substrates

Abstract: A method for growing semiconductor material on insulating or conducting substrates or in small apertures in insulating or conducting substrates is disclosed. The method comprises masking the surface of a nucleating semiconductor substrate with an appropriately apertured mask, epitaxially growing semiconductor material through the apertures and separating the mask with its grown semiconductor material from the nucleating substrate to produce either discrete crystals in a substrate or a crystal wafer on a substrate.

Electroplating solder-bump connectors on microcircuits

Abstract: A silicon wafer containing 100 to 300 microcircuits is coated with a patterned layer of glass and then a conducting layer of chromium and copper which connects, through openings in the glass, to circuit terminals and also to the silicon substrate at the scribe positions. A patterned photoresist then exposes only the terminal areas. An electroplating connection to the silicon substrate provides uniform, low-resistance current paths through the metallization at the scribe positions to the plating sites over the terminal positions for the electrodeposition of soldier.

Semiconductor wafer processing

Abstract: The continuous processing of semiconductor wafers transported through a reactor system having a series of reaction zones permitting separate process functions, with zone isolation achieved through the use of dynamically sealed vapor-purged isolation chambers. An in-line, verticaL arrangement of gas inlets and outlets and planar work supports effect a laminar flow of gaseous materials.

Low temperature silicon etch

Abstract: A MECHANICALLY POLISHED SILICON WAFER IS ETECHED TO REMOVE SURFACE DAMAGED MATERIAL AND GIVE A SMOOTH SURFACE BY ETCHING AT A TEMPERATURE OF FROM ABOUT 800 TO 1050*C. IN A GAS MIXTURE CONSISTING OF A CARRIER GAS OF H2, HE OR A MIXTURE THEREOF, A SMALL CONCENTRATION OF A GAS REACTIVE WITH SIO2 SUCH AS HF, CIF3 OR BRF5 AND A SMALL CONCENTRATION OF A GAS REACTIVE SILICON SUCH AS HBR, HI, HCL, CL2, BR2, OR I2.

Thermal print head wafer and method of making the same

Abstract: A thermal print head wafer including a dielectric substrate having one end whose sharp edges are removed (by grinding) to provide a continuous, blended surface between an intended printing surface of the substrate and opposed flat sides thereof. The blended surface has small grooves in the surface thereof, which grooves are aligned parallel to a direction in which the print wafer moves relative to a thermally responsive record medium with which the printing wafer is used. A layer of semiconductor material is deposited (by pulse spraying) on the blended surface while a portion of the substrate is heated in a furnace, and the deposited material is separated into discrete, spaced resistive elements by high-pressure spraying of abrasives at the semiconductor material through a slitted U-shaped mask. Electrical conductors (located on the opposed flat sides) of the substrate are connected to the ends of the resistive elements, enabling them to be selectively energized.

Method of making non-planar semiconductor devices

Abstract: IN THE MANUFACTURE OF A SEMI-CONDUCTOR DEVICE, A WAFER WITH AT LEAST ONE P ZONE AND AT LEAST ONE N ZONE IS POSITIONED ON A SUPPORT AND DIVIDED INTO A PLURALITY OF PARTS EACH OF WHICH IS TO CONSTITUTE A DEVICE, CHANNELS BEING DEFINED BETWEEN THE DEVICES AND P-N JUNCTIONS BEING EXPOSED IN THE CHANNELS. A CURABLE COMPOUND IS THEN POURED INTO THE CHANNELS, THIS COMPOUND BEING CAPABLE OF PROTECTING THE P-N JUNCTIONS, AND FINALLY THE COMPOUND IS CURED SO AS TO FORM A PROTECTIVE FILM OVER THE JUNCTIONS.

Radiant energy photovoltalic device

Abstract: A radiant energy conversion device which comprises a silicon slice, a silicon-to-germanium transitional region of a first conductivity type, a germanium layer of a second conductivity type and a pair of ohmic contacts. One form of the device includes an epitaxial deposition of a P-type transitional region onto a low resistivity P-type silicon slice. An N-type germanium layer is then epitaxially deposited on the transitional region. The transitional region contains an electrostatic drift field which improves the collection of charged particles. A current collecting grid is bonded to the silicon slice and a conductive support is bonded to the germanium layer.

Construction of monolithic chip and method of distributing power therein for individual electronic devices constructed thereon

Abstract: To eliminate parasitic voltage drops to electrodes of semiconductor devices built on a semiconductor chip or wafer, due to the use of an element of a voltage and current supply conductor in common for several such semiconductor devices, a separate path is diffused for each electrode, onto such chip or wafer as a built-up post of the basic semiconductor material of the chip or wafer, and the back surface of the chip or wafer is used as a relatively wide area surface as a voltage supply bus, which may also be connected to a metal base for the double purpose of establishing that surface at some selected known potential and providing a good heat sink for the chip or wafer. Generally, the potential of the metal base may be placed at ground, but need not be.