Showing papers on "Wafer published in 1972"

Process for polishing thin elements

Abstract: A process for the waxless polishing of thin fragile wafers which includes positioning a wafer on a mounting pad having a coefficient of static friction with respect to the wafer such that the wafer may be moved into frictional engagement with a polishing surface without becoming disengaged from the mounting pad. The wafer and mounting pad are continuously rotated during polishing about a central axis normal to the plane of the wafer and such continuous rotation produces improved edge-rounding of the polished wafer.

Dielectric Breakdown in Silicon Dioxide Films on Silicon II . Influence of Processing and Materials

Abstract: The breakdown characteristics of thermally grown films on Si are shown to depend on oxide thickness, substrate doping concentration, sample preparation, presence of passivating layers, and testing temperatures. The maximum breakdown strength varies as [thickness]−0.21 below 800Aa, is essentially constant from 1000 to 2000Aa, and increases slightly (8%) with increasing testing temperature in the range −196° to +300°C. The breakdown strength is only moderately affected by the dopant‐type level in the starting silicon wafer: 1020 phosphorus atoms/cm3 in the silicon reduced the breakdown strength in 200Aa thick oxides by only 20%. The initial condition of the silicon wafer, cleaning procedure, oxidation temperature, passivation layer, and postmetalization anneal are important parameters in the control of defect‐related, low‐field breakdowns, while the oxidation ambient, substrate doping, oxide thickness, metalization, and measuring temperature have little or no influence on this process.

Contacting integrated circuit chip terminal through the wafer kerf

Abstract: A test system for selectively accessing mechanically difficult to access terminals in an integrated circuit chip by the combination of an externally accessible circuit terminal formed in the wafer kerf, a conductive bus bar formed in the kerf connected to the terminal, connecting means for connecting each of a plurality of chip terminals to the conductive bus bar, means for connecting the kerf terminal to a tester, and means for selectively activating a connecting means between the chip terminal and bus bar to provide conductive signal paths from selected chip terminals to the kerf terminal.

Photolithographic mask alignment using moiré techniques

Abstract: A method is described for quick alignment of photolithographic masks over silicon substrates. Moire reflection patterns are observed from grids etched on the silicon wafer and grids located on the photolithographic masks. A restricted class of moire patterns provides information on both the direction and degree of misalignment during all phases of alignment. Alignment accuracy of 0.2 microm has been achieved even when there were separations of 30 microm between the mask and wafer. The moire patterns can be observed visually through standard mask-alignment facilities. The etched grids are found to retain their diffraction properties during the operations of reoxidation and epitaxial growth.

Method of fabricating a multiwafer electrical circuit structure

Abstract: A method of fabricating an electrical circuit structure comprised of a plurality of electrically conductive wafers stacked together under pressure to form a parallelpiped structure containing one or more active components (e.g., integrated circuit chips) as well as conductor means providing coaxial interconnections in X, Y and Z-axis directions. A stack is normally comprised of conductive wafers of different types including component wafers, interconnection wafers, and connector wafers. Z-axis interconnections, i.e., through-connections in a wafer, are fabricated directly from the wafer material itself by selective chemical etching of the wafer so as to form spaced electrically insulated solid conductive slugs within the wafer profile extending between the top and bottom wafer surfaces, with each slug being surrounded by dielectric material which supports the slug and electrically isolates it from the remainder of the wafer material. X-Y axis interconnections for electrically connecting the Z-axis slugs in a wafer in a predetermined manner are also fabricated directly from the wafer material by selective chemical etching so as to form X-Y axis conductors which are likewise contained within the wafer profile and surrounded by dielectric material providing support and electrical isolation. Highly reliable wafer-to-wafer electrical interconnections are obtained in a stack by providing malleable conductive contacts between opposing contacting Z-axis slugs in adjacent wafers, and pressure stacking the wafers so that these malleable contacts are deformed. Additional malleable contacts which are likewise deformed by the pressure stacking are also advantageously provided between other opposing portions of adjacent wafer surfaces for providing wafer-to-wafer ground interconnections. The advantages of pressure stacking are further increased by providing a uniform pattern for the Z-axis slugs and the ground interconnections on all of the wafers of a stack so as to obtain uniform distribution.

Reproducible Liquid‐Phase‐Epitaxial Growth of Double Heterostructure GaAs–AlxGa1−xAs Laser Diodes

Abstract: Highly uniform GaAs–AlxGa1−xAs double heterostructure (DH) wafers have been reproducibly grown, and when fabricated into DH laser diodes yield diodes whose current threshold densities Jth lie within ±5% of each other. Other laser parameters such as lasing wavelength and external differential quantum efficiency ηD also show the same uniformity. The DH wafers can be reproducibly grown so that these parameters lie within ±10% from wafer to wafer. The methods used to achieve these results employ a well‐designed sample holder, minimization of contaminants into the system, reproduction of oven gradients from run to run, and careful temperature control and temperature reproducibility. Using these techniques, we have been able to grow DH wafers, whose active layers are as thin as 0.14 μm. When fabricated into laser diodes, 200 mW of continuous power output has been obtained at room temperature.

Shingled array of solar cells

Abstract: A method of mounting solar cells in an array, and a solar cell array, in which the cells are arranged on thermally conductive but electrically insulative wafer and prominences so that they overlap each other in a shingled structure but their bottom surfaces are supported and remain parallel to the top surface of the mounting wafer, the array structure permitting series wiring of the cells and providing a rugged structure having a thermally conductive path from the solar cells through the mounting elements.

A Cross‐Hatch Pattern in GaAs1 − x P x Epitaxially Grown on GaAs Substrate

Abstract: A cross‐hatch pattern which appears on the surface of epitaxially grown on the substrate was studied by x‐ray diffraction techniques. The origin of this structure was determined by x‐ray diffraction topography to be a misfit dislocation array aligned along lines perpendicular to each other in the layer of graded composition. The composition profile normal to the wafer was also determined by electron microprobe analyses. Furthermore, the growth mechanism of the aligned dislocations was proposed from the fact that aligned dislocations enable a considerable reduction in the curvature of the wafer which is due to the lattice mismatch between the epitaxial layer and the substrate. The wafer having the cross‐hatch pattern was determined to be high in quality from the half width of the rocking curve.

Yield degradation of integrated circuits due to spot defects

Abstract: Economy of integrated circuit fabrication in the presence of quasi-randomly distributed spot defects is described. The distribution of the defects is represented in terms of density and modeled as follows : 1) they are randomly distributed within a limited area; 2) the density in a wafer changes concentrically; and 3) the density is normally distributed from wafer to wafer with uniform deviation throughout a wafer. The yield degradation phenomenon due to such defects has been analyzed using a computer simulation technique. The effect of density variations in a wafer and between wafers has been mainly investigated. An extensive numerical study leads to the following conclusions. 1) The deviation of the yield versus chip-area relation from the simple exponential law is influenced more greatly by the nonuniform defect distribution in a wafer than by the density variation between wafers. 2) The increase of average yield due to the density variation between wafers is sometimes offset by the decrease of the accuracy in yield prediction. Process stabilization is essential for the economical production of a few large-scale chips.

Process for laser scribing beam lead semiconductor wafers

Abstract: Microelectronic circuits are produced in semiconductor wafers with beam leads having adhering and non-adhering portions. The non-adhering portions comprise the projecting part of the beam lead. The wafer is divided into chips having beam leads by partially cutting the wafer from the reverse side with a laser beam. The wafer is initially positioned for the laser cutting using an infrared light and a vacuum for securing the wafer at the correct position prior to the laser scribing. The uncut portion of the wafer is broken and the semiconductor chips are separated. During the separation, the non-adhering portions of the beam leads become separated from adjacent chips.

Method of making an inductor chip

Abstract: A monolithic inductor chip for use in electronic circuits, especially integrated and/or hybrid micro-electronic circuits, is formed by providing a plurality of ferrite wafers each having a conductive element of generally U shape silk screened on its top surface. An end portion of each element passes through a hole in the wafer to a point on the bottom of the wafer. The various wafers are stacked in such a manner that the end portion on the bottom of one wafer electrically connects to the initial point of the U shape element on the top of the next successive wafer so that the stacked wafers define an inductive coil. The resulting stack is sintered to provide the monolithic chip.

Liquid silica source for semiconductors liquid silica source for semiconductors

Abstract: THERE IS DISCLOSED A LIQUID SILICA SOURCE FOR SEMICONDUCTOR DIFFUSIONS WHICH COMPRISES IN COMBINATION 54-64% ETHYL ALCOHOL, 11-21% ETHYL ACETATE, 13-63% TETRAETHYLORTHOSILICATE, AND 3-10% WATER AND 1-8% VINYL TRICHLOROSILANE, SAID PERCENTAGES BEING BY WEIGHT. THE LIQUID SILICA SOURCE MAY BE READILY COATED ONTO THE SEMICONDUCTOR WAFER EITHER BY PAINTING, SPRAYING OR PERFERABLY SPINNING.

Performance of GaAs Surface-Barrier Detectors Made from High-Purity Gallium Arsenide

Abstract: Gallium arsenide surface barrier diodes have been fabricated from high purity level materials. These devices have an Au surface barrier having a depletion layer thickness of from 70?mto 1 mm and an area of from 3mm2-27mm2. These devices have been operated as ?-particles, / s-ray, and ?-ray spectrometers and detectors. The best energy resolutions taken with a GaAs detector made from liquid phase epitaxial GaAs wafer were 20keV (fwhm) and 8 keV for 5.486 MeV ?-particles from 241Am and 115 keV conversion electrons from 57Co at room temperature, respectively. For room temperature applications, a simple charge sensitive preamplifier was constructed using two FETs and one OP amp. The combination of a encapsulated GaAs detector and two small semiconductor thermoelements (electrical cooling device) was studied to make a simple X-or ?-ray spectrometer. A special tiny GaAs detector was also fabricated as in vivo s-ray counting detector in biomedical applications. The energy per electron-hole pair (?) in GaAs was measured at 4.35 + 0.02 eV for ?-particles with a linear variation with bandgap energy (Eg) of 2.53 over a temperature range of 1950°K to 330°K, and 4.57 eV for conversion electrons (115keV) at 300°K, respectively. The ? vs Eg relationship was also investigated for Ge, Si, GaAs and CdTe using experimental values and led to ? = 2. 596 Eg + 0.714 (eV) with correlation coefficient of 0.999 at 300°K. The related problems for intrinsic material constant (?) are discussed for several semiconductor materials.

Apparatus for the liquid-phase epitaxial growth of multi-layer wafers

Abstract: An apparatus for the liquid-phase epitaxial growth of multilayer wafer comprising a refractory furnace tube, a boat placed in the furnace tube and having a plurality of bathes which are aligned in the longitudinal direction of the furnace tube and respectively carry solutions each containing semiconductive substances, and a holding member for holding a substrate which is arranged to succeedingly flood the substrate with the solutions so as to epitaxially grow a multi-layer wafer on the substrate. The holding member arranged to upset the substrate upon pickingup or separating of the substrate from the solution so that the solution remained on the substrate is dropped from the substrate whereby unwanted mixing of the solutions neighbouring each other can be avoided.

Apparatus for the automatic alignment of two superimposed objects, for example a semiconductor wafer and a transparent mask

Abstract: An apparatus for automatically aligning a semiconductor wafer with a mask in the manufacture of integrated circuit devices is disclosed. The mask and wafer are each provided with alignment patterns, the alignment pattern on the wafer cooperating with the alignment pattern on the mask in a unique visual manner to signify alignment. A scanning mechanism is provided for automatically scanning the alignment pattern areas and producing output signals indicative of the relative positions of the alignment patterns on the wafer and mask. Logic circuitry is provided for operating in response to any misalignment represented by the scan outout signals to compute formulae which are utilized to produce control signals for driving motor drive mechanisms to produce relative movement between the mask and wafer to bring them into alignment. Several separate alignment cycles are provided, if needed, for zeroing in on finalized alignment. A tolerance selection control circuit is provided for permitting a variation in final alignment tolerance.

Apparatus for waxless polishing of thin wafers

Abstract: A process and apparatus for the waxless polishing of thin fragile wafers which includes positioning a wafer on a mounting pad having a coefficient of static friction with respect to the wafer such that the wafer may be moved into frictional engagement with a polishing surface without becoming disengaged from the mounting pad. The wafer and mounting pad are continuously rotated during polishing about a central axis normal to the plane of the wafer and such continuous rotation produces improved edgerounding of the polished wafer.

Method of planar mounting of silicon solar cells

Abstract: A method of mounting silicon solar cells in a planar array that not only lds electrical insulation between cells but allows for a multifold increase in thermal dissipation of the cell array, comprising metallizing a wafer of beryllium oxide on each side so that the outer surface is copper, etching the wafer on one side so that the only metallized parts which remain are those on which the solar cells are to be mounted or wiring is to be attached, soldering the solar cells on the unetched copper prominences, coating the aluminum panel on which the cells are mounted with a copper layer, soldering the underside of the wafer on the upper surface of the aluminum panel with soft solder such as indium, and covering all remaining passive surfaces with a teflon F.E.P. tape the underside of which carries a layer of slver and then a layer of inconel metal.

Object handling fixture, system, and process

Abstract: A system for handling an oriented array of objects, such as integrated circuit chips, includes a fixture in which the chips are held in place by vacuum means. A chip placement tube is capable of reciprocal motion normal to the plane of the fixture to move a chip unidirectionally from its position in the array for placement on a substrate. The system further includes means for positioning a substrate precisely with respect to a chip in the array to allow its direct placement from the array. This fixture and system allows the precise orientation and alignment of semiconductor chips in a wafer to be maintained for laser dicing and chip positioning on a substrate without requiring reorientation. When combined with testing and inspection apparatus and a suitable memory, the system further allows handling and processing of chips to be minimized.

Liquid phase deposition of thin insulating and refractory film on a substrate

Abstract: It is known to deposit zirconium dioxide, ZrO2, on a substrate comprising a chip or wafer by providing zirconium oxychloride, ZrOCl2, vapor at about 550 DEG C, the chip or wafer being at 450 DEG C, in an atmosphere containing water vapor. Zirconium dioxide, ZrO2, and hydrochloric acid, HCl, are produced and a layer of the ZrO2 is deposited on the chip. The ZrO2 layer acts as a passivation material having high resistivity and very good impermeability to sodium which can be destructive of the circuit on the chip or wafer. According to this invention, the ZrO2 may be deposited on a substrate at a lower temperature from a liquid solution of the zirconium oxychloride, whereby the substrate may be paper or plastic and whereby the substrate if it includes a circuit will not be injured by the temperature needed by the prior art high temperature treatment, and therefore the possible injury to the substrate or to the circuit therein by the prior art high temperature treatment is avoided.

Method for achieving uniform exposure in a photosensitive material on a semiconductor wafer

Abstract: A method of fabricating semiconductor devices on a wafer, in which an antireflection layer is interposed between a layer of insulating material and a photosensitive layer. The use of this antireflection layer allows suppression of the optical interference between an incident light wave and a light wave that is ordinarily reflected back into the photosensitive layer. Also, this layer provides a surface to which a positive photoresist material generally used as the photosensitive layer will adhere tenaciously.

Semiconductor mass memory

Abstract: A block-addressable mass memory subsystem comprising wafer-size modules of LSI semiconductor basic circuits is disclosed. The basic circuits are intrinsically addressable and interconnected on the wafer by non-unique wiring bus portions formed in a universal pattern as part of each basic circuit. A disconnect circuit isolates defective basic circuits from the bus.

Compositions for use in forming a doped oxide film

Abstract: A doped silicon oxide-forming film is produced on a semiconductor wafer by coating the wafer with a solution prepared by the reaction of tetraethylorthosilicate with acetic anhydride in the presence of a suitable solvent. A suitable dopant species is also contained in the solution. Upon heating the wafer to diffusion temperature, a doped oxide film is formed, and the dopant diffuses from the doped oxide film into the semiconductor.

Liquid diffusion dopant source for semiconductors

Abstract: THERE IS DISCLOSED A LIQUID DIFFUSION DOPANT SOURCE FOR SEMICONDUCTOR DIFFUSIONS WHICH COMPRISES IN COMBINATION 54-64% ETHYL ALCOHOL, 15-25% ETHYL ACETATE, 7-17% TETRAETHYLSILICATE, 3-10% WATER AND 0.1-10% OF A DOPING ATOM SORUCE SELECTED FROM THE GROUP CONSISTING OF THE COMPOUNDS OF ARSENIC, PHOSPHORUS, BORON ANTIMONY, ZINC, ALUMINUM, PLATINUM, GOLD AND GALLIUM. THE LIQUID DOPANT SOURCE MAY BE READILY COATED ONTO THE SEMICONDUCTOR WAFER EITHER BY PAINTING, SPRAYING OR PREFERABLY SPINNING. AFTER DRYING OF THE COATING, DIFFUSION OF THE DOPANT ATOMS INTO THE WAFER IS READILY CONDUCTED IN A STANDARD DIFFUSION FURNACE.

Method of making insulated gate field effect transistor

Abstract: The present invention relates to an insulated gate field effect transistor and method of making same. An aluminum film is evaporated on a silicon wafer. Portions of the aluminum film are masked. The unmasked portions are anodized. The unanodized portions are removed leaving the anodized insulative portions thereon. Dopant atoms are diffused into areas of the silicon wafer which are not covered by the anodized insulative layer. The anodized insulative layer acts as a diffusion mask, to form source and drain regions in the silicon wafer, and to thus delineate a gate insulator layer between the source and drain regions by the act of diffusion. A second aluminum film is evaporated over the silicon wafer. The portions of the areas of the second aluminum film over the source and drain regions, and the area of the second aluminum film over the aligned gate insulator layer are masked. The unmasked portions of the second aluminum film are anodized to delineate an aligned gate electrode over the aligned gate insulator layer and to delineate source and drain electrodes in contact with the source and drain regions. An insulated gate field effect transistor is thus formed.

Manufacture of assorted types of lsi devices on same wafer

Abstract: Multiple LSI (Large Scale Integrated) semiconductor devices (chips) of assorted types (different design and function, representing different assembly parts or devices) are fabricated in aggregate on one integral wafer crystal. A multitype composite mask or procedural equivalent is used. In specific instances this results in distinct savings in production apparatus, test apparatus, procedures and materials usage; e.g., low quantity multitype custom production runs. Devices of each desired type are scheduled for production in prescribed areas of the wafer. The areas are laid out as a function of pre-assessed yield probabilities and pre-established quantity requirements for the individual types. The wafer areas are allocated so as to optimize potential device yields in each type category; in the ultimate case to yield at least one useful device of each type.

Electronic component mounting wafers for repeated connection in a variety of circuit designs

Abstract: There is disclosed a plurality of wafers, each having a multiplicity of sets of electrically conducting pads, the pads within one set being electrically connected together and electrically isolated from each of the other sets. At least one pad in each of the sets has a connecting area adapted to receive and be soldered and unsoldered repeatedly to a conductive mounting lead of an electronic component. At least another pad in each of the sets having a connecting area adapted to receive and be soldered and unsoldered repeatedly to a conductive interconnecting lead which may connect one set of conducting pads with another. Each of the sets of pads has a thickness and shape which provides an electrically conducting path of sufficient length between each pad connecting area in the set to substantially isolate from one connecting area excessive and damaging heat from soldering and unsoldering conductive leads at another connecting area.

Solar cell array

Abstract: A solar cell planar array fabricated by a method from the solar cells to the mounting panel. An electrically insulative, thermally conductive wafer is soft-soldered to the surface of the metallic mounting panel. The top surface of the wafer bears spaced electrically insulative, thermally conductive prominences thereon. The solar cells are attached on top of the prominences.

Methods for making semiconductor pressure transducers and the resulting structures

Abstract: A semiconductor pressure transducer comprises a first portion of semiconductor material containing therein a hole, a second portion of semiconductor material placed over the top of said hole and strain sensitive electrical components formed on a selected surface of said first or said second portions of semiconductor material so as to be responsive to variations in pressures incident upon said transducer. A plurality of such semiconductor transducers are formed using semiconductor processing techniques by forming a plurality of holes in a first wafer of semiconductor material, forming a plurality of strain sensitive electrical components on a selected surface of either said first wafer or a second wafer of semiconductor material, then joining the first and second wafers of semiconductor material in a controlled pressure environment so as to seal said plurality of holes and finally separating the transducers from the composite structure.

Isolation mounting for semiconductor device

Abstract: An isolation mounting for a semiconductor device includes a metal heat sink plate to receive heat from the semiconductor device and insulating means to electrically isolate the semiconductor device from the plate which receives the heat. A metal fastener presses the semiconductor device against an insulating wafer which is in turn pressed against the heat sink plate. An insulating liner separates the fastener electrically from metal of the semiconductor device.

Apparatus for inducing eddy current in a semiconductor wafer for measuring the electric conductivity or resistivity thereof

Abstract: An apparatus for measuring electric conductivity or resistivity of a semiconductor wafer with no electric contact to the wafer, which comprises an exciting circuit including a first exciting coil for measuring, and a second exciting coil for compensation, which are connected in series to each other, and an oscillator for supplying an alternating current to the first and second exciting coils. A detecting circuit has a first detecting coil which is positioned spaced apart from the first exciting coil to form a gap therebetween, the wafer being inserted in the gap for measurement, and a second detecting coil for compensation which is connected in series to the first detecting coil and is magnetically connected to the second exciting coil, thereby a differential output being obtained between each end of the first, and second detecting coils. A bandpass filter eliminates higher harmonics and noise component and is contained in the output of the detecting circuit, and a phase shifter shifts the phase of the output of the bandpass filter to the phase of the voltage induced in the second detecting coil. A synchronous rectifier means rectifies synchronously the output of the phase shifter with reference to the output of the detecting circuit, and an operation circuit means is provided to obtain an output proportional to the electric conductivity or resistivity of the wafer from the output of the synchronous rectifier means and data concerning the thickness of the wafer. An indicator means indicating the output of the operation circuit means.