Showing papers on "Wafer published in 1974"

Thin film electrochemical electrode and cell

Abstract: A thin film polarographic oxygen sensor, in which a number of thin film microcathodes are deposited in holes in a thin film layer of silicon dioxide formed on a silicon substrate. A single thin film anode layer is deposited on the insulating layer and is insulated thereby from the cathodes. Preferably the microcathodes and the anode are located in a well in the thin film insulating layer, the well being filled flush to its surface with electrolyte, and having a thin film polymer filter membrane deposited thereover. Contacts to the anode and cathodes may be punched through a thin film insulating layer on the back of the wafer, the cathode contact being thereby connected to the substrate, and the anode contact being insulated from the substrate by an encircling thin film layer of silicon dioxide and extending through to the anode metallization layer. With appropriate choice of electrode, electrolyte and membrane materials, the cell may also be used as a pH sensor, a CO 2 sensor, a specific ion sensor, or to detect or sense other substances in solution. Single electrode units may also be formed by depositing thin film electrode materials on appropriate substrates.

Apparatus for processing semiconductor wafers

Abstract: Circular wafers of semiconductor (silicon) are chemically treated, e.g., etched, by supporting the wafers vertically by contacting their edges with annularly grooved drive rollers, immersing the supported wafers in a body of chemical medium (e.g., etchant solution) for treatment, and rotating the wafers by rotation of the drive rollers while the wafers are immersed in the body of medium to uniformly and precisely treat the surfaces of the wafers. Apparatus for effecting such precision etching includes an etchant tank, a wafer rack including the drive rollers which support the edges of the wafers in vertical face-to-face relationship, the rack being lowered into the etchant to immerse the wafers. Means is disclosed for rotating the drive rollers for rotation of the immersed wafers and provision is included for circulating the etchant for causing uniform flow thereof past the rotating wafers. A heat exchanger maintains the etchant substantially at a predetermined temperature.

Self-configurable circuit structure for achieving wafer scale integration

Abstract: A self-configurable circuit structure and method for forming the same, for achieving wafer scale integration including the combination of an integrated circuit wafer having an input and an output, wafer control means to provide test and operational modes, at least one unit circuit on the wafer connected to the wafer control means, coupled between the wafer input and output. The unit circuit includes a semi-conductor chip, test means for functional testing of the chip and circuit control means responsive to the output of the test means to intercouple the unit circuit if it is properly functioning between the wafer input and output to form a functional circuit.

Liquid encapsulated integrated circuit package

Abstract: A liquid encapsulated high density integrated circuit package which serves as a complete computer basic system module having both logic and memory circuits in the same package. This unit takes advantage of improvements in the integrated circuit art to minimize the number of physical units required to provide the desired memory capacity while simultaneously maximizing density and thereby minimizing signal path length. Basically the package contains a plurality of stacked semiconductor wafers each of which provides either integrated memory or logic functions. Each semiconductor wafer is mounted on an insulated wafer carrier and is connected to stacking pins around the perimeter of the carrier via a series of radial interconnection which are flexible expansion leads disposed around the outer edge of the wafer. Each wafer is floatation mounted by attaching only its center to the carrier to minimize the stress effects of a thermal expansion mismatch between the wafer, the carrier, and the radial interconnections. The carrier on which the wafer is mounted is constructed to mechanically secure and support the wafer at its physical center, to provide electrical contact to the wafer substrate, to provide support of electrical stacking pins which connect with stacking pins on adjacent carriers, to provide support for the radial interconnection expansion leads extending between pads on the wafer and the stacking pins and to minimize the effects of thermal mismatch in the structure. A finned housing encloses the stacked wafers and carriers and is hermetically sealed to a header having feed through termination pin such that the package can contain a liquid coolant which aids in the transfer of heat between the wafers and the finned housing thus maximizing the dissipation of heat from the wafers.

Vapor deposition method of forming low cost semiconductor solar cells including reconstitution of the reacted gases

Abstract: The disclosure relates to a method of upgrading metallurgical grade silicon to semiconductor grade for making low cost silicon devices and particularly solar cells. This is accomplished by passing conductive fibers such as graphite or the like which are compatible with the later processing steps through an area which is cooled below 700° C and which contains silicon difluoride and a proper N-type dopant. At these temperatures, the silicon difluoride gas will break down into pure silicon which will deposit onto the fiber with the formation of silicon tetrafluoride gas which is then recycled into a further chamber. In the further chamber, the gaseous silicon tetrafluoride is mixed with the impure metallurgical grade silicon at temperatures above 700° C to form the silicon difluoride gas which is then fed into the former chamber for deposition of pure silicon onto the continuously moving fibers of graphite or the like. A p-type layer can then be formed over the n-type layer in any standard manner, such as by then passing the coated fibers through a further reaction chamber wherein p-type dopant is diffused into the top surface of the n-type layer that has been formed. The dopants alternatively could be added in the gas stream of SiF 4 or the p-layer formed by ion implantation. In this way, relatively inexpensive p-n junction devices are formed without the requirement of purifying, cutting and polishing a silicon slice in the standard manner.

Tungsten metallization for LSI applications

Abstract: It is shown that MOS–LSI devices can be satisfactorily metallized with tungsten thin films using the rf-diode sputtering technique. The apparatus used consisted of a roots-blower and a Vacion pumped belljar system equipped with an 8-in. diam CVD W-cathode and a W-substrate table (anode) to which a dc bias could be applied. The control substrates were oxidized silicon wafers in which the back-oxide was removed to facilitate proper application of the bias. The effect of sputtering power (200–400 W) and of substrate bias (−200−+250 V) was studied on the deposition rate, substrate temperature, and various properties of the film such as electrical resistivity, stress, impurity concentration, constitution, and microstructure. The present process of W-film depostition has been found to offer several advantages. Low-power and low-voltage operation results in high quality MOS-compatible W-films. Substrate heating during the sputter deposition is kept to a minimum, thereby eliminating any undesirable metallurgical ...

Method of reclaiming a semiconductor wafer

Abstract: A method of reclaiming a semiconductor wafer wherein wafers which have been rejected due to electrical failures or visual defects can be processed to form a purer wafer capable of providing above average yields The method comprises the steps of gettering to draw undesired point defects (impurities and vacancies) toward the wafer surface and chemical etching to remove most of the point defects whose presence in silicon would lower semiconductor yields Other steps include grinding the back surface of the wafer to form an insitu getter region and finally polishing the front of the wafer to form a strain-free mirrorlike finish

Polycrystalline silicon pressure transducer

Abstract: A semiconductor pressure transducer having a polycrystalline silicon diaphragm providing an extremely pressure sensitive and temperature stable device, and a method of making the same. The polycrystalline silicon can easily be vapor deposited on an etch resistant layer covering a surface of a wafer or base, preferably monocrystalline silicon. Such vapor deposition of the polycrystalline silicon more accurately and consistently defines the thickness of the diaphragm than can be obtained by grinding or etching. A pressure responsive resistor formed in the diaphragm is automatically electrically isolated by the comparatively high resistivity of the polycrystalline silicon. Accordingly, PN junction isolation and passivating oxides on the diaphragm are not required thereby resulting in increased temperature stability.

Fully ion-implanted bipolar transistors

Abstract: Technology for the fabrication of fully ion-implanted bipolar transistors with arsenic emitters and boron bases is described. This technology results in extremely uniform distributions of electrical parameters, e.g,, h FE = 113 with a standard deviation of 1.3 across a wafer. In addition, it can produce a wide range of doping profiles and hence, a wide range of device performance. Using very similar processing schedules, transistors with h FE from 20 to >5000 and with f T 's from 1.5 to 8.1 GHz have been made. The features of implanted arsenic which make it an excellent emitter are: 1) it can be implanted to high doses with only a small deep side tail which has a negligible effect on the typical transistor base; 2) because of the concentration dependence of its diffusion constant, it forms a very abrupt profile after diffusion; and 3) when diffused a short distance (∼1000 A) away from the implanted region, high-lifetime material can be incorporated into the emitter and hence, high-gain low-leakage transistors can be made. When the arsenic emitter is combined with a double-peaked boron-implanted base, precise independent control of the active and inactive base properties of the device can be achieved. This independence allows considerable latitude in the choice of device parameters for fully implanted bipolar transistors.

Dielectrically isolated semiconductor devices

Abstract: The invention is a method of fabricating dielectrically isolated semiconductor regions adapted for the construction of an integrated circuit on an epitaxial wafer wherein the epitaxial wafer has a first layer of monocrystalline n+ type silicon of a predetermined thickness and a second layer of epitaxially deposited n-type silicon which is substantially thinner than the first layer. A layer of silicon dioxide is grown on the back side of the first layer of the wafer and a layer of polycrystalline silicon is deposited onto the silicon dioxide layer. An aluminum oxide mask is formed defining a plurality of grooves around active semiconductor regions within the n-type silicon layer. The grooves are formed by a sputter etching process. Silicon dioxide is thermally grown within each of the grooves exposed by the sputter etching process to dielectrically isolate the active semiconductor regions after which semiconductor devices may be formed in each of the active semiconductor regions.

Backside laser dicing system

Abstract: A wafer of semiconductor material having a plurality of units defined on its face is subdivided by treating the wafer, on its back or reverse side, in the kerf regions between the units, where division of the units is desired, such that the material of the wafer in the treated kerf regions is converted to a material having a breaking strength lower than the breaking strength of the semiconductor material.

Method for filling grooves and moats used on semiconductor devices

Abstract: A process is disclosed for filling grooves, moats, and channels formed by both channel and anisotropic etching techniques. Basically the process is a two-step process to be performed on a wafer in which a channel and/or a moat has been formed. A P+ (boron) doped oxide is placed in the grooves or moats using spinon techniques followed by a uniform deposition of polycrystalline silicon over the entire wafer. Due to the spinning effects the P+ doped oxide is collected mostly in the grooves or moats. The P+ doped oxide that remains outside of the grooves and/or moats is removed using standard photolithographic procedures. The wafer is now heated to a temperature sufficient to drive the boron impurities from the P+ doped oxide into the polycrystalline silicon. A portion of a polycrystalline silicon now becomes heavily P+ doped. The remaining polycrystalline silicon remains undoped. The wafer is then etched by an etchant which effectively stops when the material being etched is highly P+ doped. In this manner a portion of the remaining undoped polycrystalline material is removed and the highly doped polycrystalline material is left in the channels and/or moats. The above can be repeated until the moats or channels are completely filled.

Beam lead formation method

Abstract: The present disclosure is directed toward a method for making semiconductor devices having beam leads for electrical connections to external terminals. An undercoating metal film is deposited directly or via a protective film on a semiconductor wafer on which interconnections are formed together with electrode pad or contact areas. After subsequent deposition of an upper metal film, beam leads are formed in a desired pattern in a manner to contact with and extend from the electrode areas. The final step is to apply physical force to the semiconductor wafer such that the undercoating metal film serving also as a portion of the beam leads is forcibly spaced away from the major surface of the semiconductor wafer.

Semiconductor wafer alignment apparatus

Abstract: An apparatus for treating a wafer of semiconductor material so that individual devices which may be simple devices or complete complex integrated circuits defined on the front surface of the wafer can be easily separated from the wafer. The apparatus aligns the wafer to a fixed reference position, inverts the aligned wafer to expose its backside and transfers it with controlled motion to a set position under a laser beam apparatus. The laser beam scans the backside of the wafer to create in the kerf area between each of the devices an easily fractured region. While maintaining the wafer alignment the laser treated wafer may be transferred to a flexible pressure sensitive tape tensioned across the frame which maintains the wafer alignment. The wafer, while on the frame can be tested, fractured into respective individual devices, and selectively removed from the tape.

Semiconductor wafer transfer device

Abstract: A device for permitting the simultaneous transfer of a plurality of silicon wafers from one wafer carrier to another, and particularly for permitting a mass transfer between carriers having different wafer spacings The device comprises two rectangular frames with a portion of the upper frame extending into the lower frame Both frames are provided with a plurality of wafer slots although in the lower frame there is a greater number of slots and they are more closely spaced than in the upper frame Each frame is adapted to interface with and be releasably secured to a carrier having a like number of wafer slots The upper frame is slidable within the lower frame and means are provided to register its slots with different groups of the slots in the lower frame With such an arrangement, wafers from a carrier secured to the upper frame can be transferred to a particular group of slots in a carrier secured to the lower frame after which the upper frame can be moved so that its slots register with a different group of slots in the lower frame whereby another carrier can be secured to the upper frame and its wafers transferred to a different group of slots in the carrier secured to the lower frame

Integrated optical signal processing system

Abstract: An electrooptic thin film wave guide structure is used to deflect an incident optical beam such as a laser beam. This structure is made of an electrooptic thin film material of high resistivity which can be obtained by either epitaxial growth on a conducting substrate or by mechanical thinning of a bulk wafer. A single electrode or multiple electrodes are fabricated on the thin film material. By applying a voltage to the electrode or electrodes, a refractive index change is produced in the thin film material and the incident laser beam is deflected within the plane of the thin film material. By forming a plurality of electrodes on the thin film material and applying properly programmed voltage wave forms to the electrodes, the refractive index profile in the plane of the thin film material may be varied to produce a high speed optical switching function. This optical switch can be used as a multiplexing terminal to steer a single or multiple beams in either time, space or frequency domains.

Wafer elements for progressing cavity stators

Abstract: A progressive cavity motor with a bifoil stator assembled in a straight-sided wafer array and methods of formation of said stators.

Deep levels in gallium arsenide by capacitance methods

Abstract: The three capacitance methods, i.e., TSCAP, PHCAP, and transient capacitance measurements, are applied to determine electronic properties of deep levels inn-GaAs. In the boat-grown wafer detected are the 0.30 eV electron trap withNT=3.6×1016 cm−3 andSn=2.4×10−15 cm2, and the 0.75 eV electron trap withNT=2.0×1016 cm−3 andSn=1.2×10−14 cm2. In the epitaxial wafer, the 0.45 eV hole trap is detected withNT>1.5×1013 cm−3 andSp=1.4×10−14 cm2 as well as the 0.75 eV electron trap withNT=2.4×1013 cm−3.

Semiconductor device manufacture

Abstract: A semiconductor wafer is electrostatically clamped against a support by positioning an intermediate solid dielectric layer therebetween and applying a potential difference, thereby firmly and evenly clamping the wafer for photoresist or ion beam implantation operations.

Method for fabricating glass-backed transducers and glass-backed structures

Abstract: A glass or other dielectric backed transducer structure is formed by utilizing a series of processes including at least one electrostatic bond. The processes enable one to bond a semiconductor wafer to a dielectric as a glass wafer. Then by selectively removing certain conductively semiconductor, one obtains a "thin ribbon" piezoresistive bridge secured to a thin glass wafer. The resultant structure is entirely unanticipated by the prior art. A glass part is also formed by electrostatically bonding a glass wafer to a semiconductor wafer, polishing the glass to a desired depth, masking the polished glass layer according to a desired pattern representative of the glass part, etching away all the glass except the desired pattern, and thence removing all the semiconductor.

Method of preparing high yield semiconductor wafer

Abstract: The method of preparing a semiconductor wafer introduces a controlled amount and distribution of lattice damage to the wafers prior to product fabrication processing steps. Semiconductor product performance characteristics improve when excess vacancies and contaminant impurities are drawn away from the pattern side of a wafer to affix themselves to the lattice damage on the reverse side of the wafer. The method includes applying an abrasive material to the backside of a rotating wafer to form a substantially circular pattern of lattice damage. The resultant distribution of lattice damage retards wafer warpage and breakage. The method lends itself to preparing virgin wafers and reclaiming used semicondcutor wafers.

Method for packaging semiconductor devices

Abstract: An improved method of packaging semiconductor devices and dice which comprises coating a semiconductor wafer with a polyimide film, etching selected areas of the polyimide film from the surface of the wafer, separating the wafer into a plurality of semiconductor dice wherein each of the dice have electrical contacts to circuits within the device and making ohmic electrical connection with the electrical contacts on the dice.

Method of positioning a semiconductor wafer for contact printing

Abstract: A non-planar semiconductor wafer chuck having a plurality of outwardly extending channels in the chuck face and a plurality of vacuum/pressure ports extending through the chuck and communicating with the face thereof. When a semiconductor wafer is positioned with respect to an overlying photomask by the chuck, atmospheric pressure is applied to the centrally located port or ports and a vacuum is applied to the peripheral ports of the chuck. The resulting pressure differentials acting in concert with a surrounding vacuum chamber causes the central portion of the wafer to rise against the photomask while the peripheral portions of the wafer are drawn down into the channels. At this point in the operational sequence, the normally trapped nitrogen can escape through breaks in the peripheral seal between the mask and wafer which are formed by the downwardly extending wafer surface in each channel. Thereafter, pressure is applied to all of the ports to press the wafer firmly against the overlying photomask for subsquent exposure.

Method for forming regions of predetermined thickness in silicon

Abstract: A method for forming thin regions of predetermined thickness in a silicon wafer which comprises the steps of applying an etchant resist mask on the faces of the wafer, opening a slot of predetermined width in the mask on one face to expose the underlying silicon, removing the mask from all areas of the other face where the thin regions are to be formed including removal opposite said slot, etching the wafer until the back surface of the thin region reaches the groove etched at the slot and then quenching the etch.

Processing apparatus for thin disc-like workpieces

Abstract: Apparatus is provided for facilitating the processing of thin, disc-like workpieces such as silicon wafers, integrated circuit masks and the like which includes an improved slide mechanism for transferring workpieces to be processed from a workpiece-containing supply receptacle to the processing area, and thereafter to a receiving receptacle so that the transportation of a workpiece to be processed occurs at the same time that a workpiece which has already been processed is removed from the processing area. A carousel arrangement is provided for atuomatically providing new workpiece receptacles as required for fully automatic, continuous processing.

Electrolytic etching and electron mobility of GaAs for FET's

Abstract: An electrolytic etching technique for n-GaAs is presented. The procedure is applied to post-growth etching of FET wafers to achieve uniformly thin layers from excessively thick and nonuniform material. Measurements on a Hall sample, thinned by this technique, show mobilities in good agreement with theoretical bulk mobility calculations for films as thin as 2100 A. From Hall measurements on layers covered by the anodic native oxide, it is determined that the oxide interface traps 3·9 × 1011 electrons per cm2 more charge than the as-grown surface.

Wafer treatment apparatus

Abstract: An isolation lock for a beam treating chamber includes an evacuable lock having a top entrance closure and a bottom exit closure and adapted to receive a wafer therein. The bottom closure being operable to an inclined position in alignment with an inclined receiver whereby to gravity feed said wafer onto the receiver. The receiver includes means to retain said wafer in a fixed position thereon and is movable to dispose the fixed wafer for beam treatment within the chamber.

Josephson tunneling through locally thinned silicon wafers

Abstract: We have made and tested Josephson junctions in which tunneling takes place through a locally thinned region in a single‐crystal silicon wafer. An etching technique is used to produce a square uniform thinned layer, 87.5 μm on a side and ≈400 A thick. After removal of the oxide layer, superconducting metals are deposited on both sides. Temperature and magnetic field dependences of the critical current, as well as the magnitude of the current, conform very closely to the theory for a Josephson tunnel junction. This is the first type of Josephson junction employing a barrier which is accessible for modification prior to deposition of the superconducting electrodes.

Diaphragm formation on silicon substrate

Abstract: A method of making thin diaphragms having an accurately controllable thickness for semiconductor pressure responsive devices. An oxide coating is thermally grown in selected regions on the front side of a silicon wafer. The oxide extends into the wafer at an extremely accurate and controllable depth to form a groove in the wafer front side defined by the selected regions. Portions of the wafer are then etched from the back side until the bottom of the groove is reached thereby providing a diaphragm having a thickness equal to the accurately reproducible depth of the groove.

Apparatus for cleaning thin, fragile wafers of a material

Abstract: Apparatus is disclosed by which a number of thin, disc-like wafers are moved in a linear path and fed into such path on a discrete basis from a supply or feeding station. The individual or discrete wafers are moved into engagement with a pair of endless belts which, in effect, define the linear path and are arranged one over the other with the facing portions of the belts being spaced apart by at least the diameter of the wafers to be interposed therebetween. As the wafers are moved through the linear path by the belts, they are moved between pairs of brushes, each of a pair being rotatably mounted on a respective side of the path for engaging and cleaning the surfaces of the wafer, the pairs of brushes extending in the direction of movement of the wafers. The belts and the brushes are coupled to drive means such that the rotary forces applied to the surfaces of the wafers by each pair of brushes is nullified to the extent that rotation of the wafers in one direction and movement along the path by the belts is not inhibited.