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Showing papers on "Wafer published in 1975"


Journal ArticleDOI
TL;DR: In this paper, a new experimental technique is described for studying the relationship between the direction of growth of a crystal surface and the meniscus at the solid-liquid-vapor junction.

142 citations


Patent
12 Dec 1975
TL;DR: In this paper, the authors proposed a method for reducing the consumption of deleterious materials used in the manufacture of semiconductor devices comprising the steps of supporting a semiconductor wafer.
Abstract: The invention relates to a method for reducing the consumption of deleterious materials used in the manufacture of semiconductor devices comprising the steps of supporting a semiconductor wafer, supplying a predetermined volume of said materials onto the surface of said wafer to form a meniscus contained body of said materials less than the normal meniscus formed by the particular material, maintaining said wafer in a static condition during the desired reaction period, sensing the completion of said reaction and spinning said wafer upon completion of said reaction to remove reaction products and terminate the reaction. Accordingly, this invention is directed at significantly reducing the initial cost of the processing fluids and the large investment and maintenance costs needed to provide the means for recovering precious materials in the fluid waste, and for the environmental disposal of corrosive waste materials resulting from the use of the fluids in integrated circuit manufacture.

120 citations


Journal ArticleDOI
TL;DR: Anisotropic etching of silicon with the hydrazine water mixture is studied and characterized for its practical use in integrated circuit technology in this paper, where the optimal temperature for the etching process is found to be 100°C for both simple temperature control and high quality etching.
Abstract: Anisotropic etching of silicon with the hydrazine‐water mixture is studied and characterized for its practical use in integrated circuit technology. The solution is applied to {100} wafers where the etch presents a v‐shaped cross section limited at the side‐walls by {111} planes and at the bottom by a {100} plane. The etching process is evaluated in terms of the etch rate of the {100} plane, quality of side‐walls and bottom surface, and corner rounding. It is shown that the results are both concentration and temperature dependent. The optimal temperature for the etching process is found to be 100°C for both simple temperature control and high quality etching. It is also shown that the optimal mixture concentration must be choesn according to the particular use of the anisotropic etching. The optimal volume concentrations of hydrazine for the various applications are: 65% for VMOS devices and for v‐groove isolation rings, 70–80% for two‐level structures with flat bottom surface, and for electrode and sensor fabrication.

109 citations


Patent
Warwick William A1
20 Oct 1975
TL;DR: In this paper, a power bus element for use in large scale integrated circuits is described, each bus element consists of a chip of silicon having two levels of metallization thereon, one acting as an earth (or ground) return plane and the other providing power voltages.
Abstract: A power bus element for use in large scale integrated circuits is described. Each bus element consists, for example, of a chip of silicon having two levels of metallization thereon, one acting as an earth (or ground) return plane and the other providing power voltages. Dependent contacts on the chip make selective contact with metallization over the surface of the semiconductor wafer on which the chip is mounted. A power distribution line consists of a number of such bus elements linked together.

87 citations



Journal ArticleDOI
K.L. Konnerth1, F.H. Dill
TL;DR: In this article, a system has been developed which permits the measurement of dielectric film thicknesses in-situ during development or etching processes, which can be extended to growth or deposition processes.
Abstract: A system has been developed which permits the measurement of dielectric film thicknesses in-situ during development or etching processes. This can be extended to growth or deposition processes. Two examples of its uses are presented: the determination of the thickness of phosphosilicate glass layers on silicon dioxide coated silicon wafers by making use of the etch rate differences, and the monitoring of photoresist thickness during development to characterize the photoresist development process.

70 citations


Patent
30 Jun 1975
TL;DR: In this paper, a microwave field effect transistor (FET) was proposed to reduce thermal resistance, lowered source lead inductance, and lowered gate series resistance, together with concomitant performance improvements, through the use of a novel source electrode connection which comprises a deposited or plated through metallic contact extending from the bottom of the wafer, through a hole in the substrate and epitaxial layer, to the underside of the source or other electrode which is deposited on the top side of the epitaxially layer.
Abstract: A microwave field effect transistor (FET) comprises source, gate, and drain electrodes deposited on an epitaxial layer grown on a semi-insulating substrate. The FET has lowered thermal resistance, lowered source lead inductance, and lowered gate series resistance, together with concomitant performance improvements, through the use of a novel source electrode connection which comprises a deposited or plated through metallic contact extending from the bottom of the wafer, through a hole in the substrate and epitaxial layer, to the underside of the source or other electrode which is deposited on the top side of the epitaxial layer. The chip, comprising the substrate, epitaxial layer, and top electrodes, is mounted on a heat sink. The chip's underside, including the bottom surface of the plated through source contact, is conductively bonded to the top surface of the heat sink.

69 citations


Patent
28 Jul 1975
TL;DR: In this paper, an array of fluid tight partitions are sealed at their outer peripheries to the adjacent support structure, and compliant portions of the partitions are individually coupled to individual ones of the spring structures for movement therewith.
Abstract: Solid state leaf spring pressure transducers are fabricated by batch photolithographic and etching techniques from a monocrystalline material, such as silicon. The leaf spring structures include elongated gaps separating adjacent leaf spring leg portions from each other and from a surrounding support structure defined by the intervening region of the wafer disposed inbetween adjacent leaf spring structures. An array of fluid tight partitions are sealed at their outer peripheries to the adjacent support structure. Compliant portions of the partitions are individually coupled to individual ones of the spring structures for movement therewith. In one embodiment, the gaps between adjacent leg portions of the individual springs and the surrounding support structure are sealed by a fluid tight web deposited over the major face of the wafer containing the batch of spring structures. In another embodiment, a web or membrane which is deposited or formed over the major face of the wafer has corrugated diaphragms formed therein. In another embodiment, a membrane is deposited over the major face of the wafer containing the batch of spring structures. In another embodiment the partitioning structure comprises a second wafer sealed over the first wafer.

69 citations


Patent
Yoshitomo Kojima1, Hiroshi Suga1
12 Nov 1975
TL;DR: In this article, an apparatus for forming grooves in a semiconductor wafer by the use of a laser beam includes a movable stage on which the wafer is mounted and a transparent member mounted on the stage in a sealed manner and covering the Wafer.
Abstract: An apparatus for forming grooves in a semiconductor wafer by the use of a laser beam includes a movable stage on which the wafer is mounted and a transparent member mounted on the stage in a sealed manner and covering the wafer A liquid is introduced into the space defined between the wafer and the transparent member

67 citations


Patent
Cuomo Jun Salvatore Ralph1
24 Nov 1975
TL;DR: In this article, an apparatus for retaining a semiconductor wafer in a predetermined position or orientation to permit dicing of the wafer into discrete semiconductor chips of a predetermined size without dislocation of the chips during the dicing operation, the chips being arranged in columns and rows with a kerf area intermediate adjacent chips.
Abstract: This patent discloses apparatus for retaining a semiconductor wafer in a predetermined position or orientation to permit dicing of the wafer into discrete semiconductor chips of a predetermined size without dislocation of the chips during the dicing operation, the chips being arranged in columns and rows with a kerf area intermediate adjacent chips. The apparatus comprises a base member having a semicondcutor wafer positioning area with a connection to the base member for applying the vacuum to a plurality of spaced apart apertures in the wafer receiving area, the apertures corresponding to the location of the chips. A cover plate, adapted for superimposition of the wafer receiving area, includes a plurality of interdigitated ribs and slots, the slots extending through the cover and dimensioned for alignment with the kerf area of the wafer, the ribs having strips of compressible material underlying the ribs for superimposed pressing relation on the wafer so that when a wafer is being cut through the slots along the kerf area, the vacuum being drawn coupled with the pressing engagement of the strips on the wafer inhibit dislocation of the chips during the dicing operation.

61 citations


Journal ArticleDOI
TL;DR: In this paper, a static technique for a very accurate measurement of charge, surface potential, low−frequency capacitance, interface charge, and interface state density in MOS structures is presented.
Abstract: A new static technique for a very accurate measurement of charge, surface potential, low−frequency capacitance, interface charge, and interface state density in MOS structures is presented. A comparison with the conductance method is made. For a 〈111〉−oriented n−type silicon wafer, oxidized in dry oxygen and annealed in hydrogen, the distribution of the interface state density is shown over an energy range of 0.9 eV within the energy gap.

Patent
24 Jun 1975
TL;DR: In this paper, the authors describe procedures for fabricating silicon devices which prevent the formation and activation of stacking fault nucleation sites during high temperature processing steps, such as steam oxidation of silicon wafers.
Abstract: Described are procedures for fabricating silicon devices which prevent the formation and/or activation of stacking fault nucleation sites during high temperature processing steps, such as steam oxidation of silicon wafers. The procedures, which take place before such high temperature steps, include forming on the back surface of the wafer a stressed layer and then annealing the wafer for a time and at a temperature effective to cause the nucleation sites to diffuse to a localized region near to the back surface. Illustratively the stressed layer comprises silicon nitride or aluminum oxide. Enhanced gettering is achieved if, prior to forming the stressed layer, interfacial misfit dislocations are introduced into the back surface by, for example, diffusion of phosphorus therein. Following the gettering step(s) on the back surface, conventional procedures, such as growing epilayers and/or forming p-n junctions, are performed on the front surface of the wafer.

Patent
06 Mar 1975
TL;DR: In this article, a test fixture used in a test system for determining the merit or electrical integrity of small semiconductor chips, diced from a semiconductor wafer having a large number of chips, each chip being a high circuit density device.
Abstract: The invention relates to apparatus for the testing of high circuit density devices fabricated by large scale integration techniques. More specifically, the invention is directed to a test fixture used in a test system for determining the merit or electrical integrity of small semiconductor chips, diced from a semiconductor wafer having a large number of chips. Each chip being a high circuit density device, e.g., a small monolithic semiconductor structure having a large number of closely spaced circuits thereon and therein.

ReportDOI
01 Feb 1975
TL;DR: In this paper, the authors describe the properties of devices with respect to resistivity, dopant profiles, crystal defects and contaminants, Oxide film characterization, test patterns, Photolithography, Epitaxial layer thickness, Wafer inspection and test, Interconnection bonding, Hermeticity, thermal properties of device.
Abstract: : ;Contents: Resistivity; dopant profiles; Crystal defects and contaminants; Oxide film characterization; Test patterns; Photolithography; Epitaxial layer thickness; Wafer inspection and test; Interconnection bonding; Hermeticity; Thermal properties of devices.

Patent
29 Dec 1975
TL;DR: In this article, a method and apparatus to improve the capabilities of automatic and semi-automatic diode, integrated chip, and wafer probers is presented, which is accomplished through an electronic logic circuit triggered by electrical contact of the probe as opposed to a mechanical sensor.
Abstract: Disclosed is a method and apparatus to improve the capabilities of automatic and semi-automatic diode, integrated chip, and wafer probers Prober contact with the upper surface of the wafer to be tested is accomplished through an electronic logic circuit triggered by electrical contact of the probe as opposed to a mechanical sensor This improved surface position signal is supplied to additional digital logic circuitry to operate a vertical axis control mechanism which precisely locates the probes relative to the wafers that will be tested Thus, prober contacts with test wafers are positively and accurately made improving the reliability of the test stage of wafer production

Journal ArticleDOI
TL;DR: In this paper, anisotropic etching of silicon single-crystal wafers and spheres using 10−M potassium hydroxide as the etchant was studied and the angles of inclination varied with azimuthal position and could be correlated with the slow-etch directions measured from an etched sphere.
Abstract: Studies of the anisotropic etching of silicon single−crystal wafers and spheres were conducted using 10−M potassium hydroxide as the etchant. The etch rates along the major slow−etch directions were measured. The sides of circular mesas etched into (111), (110), and (100) wafers were found to be inclined to the wafer surface. The angles of inclination varied with azimuthal position and could be correlated with the slow−etch directions measured from an etched sphere. A method was developed to predict these angles of inclination for surfaces of varied orientation using the rate of etching data and angular measurements from an etched sphere.

Patent
29 Dec 1975
TL;DR: In this paper, a shadow mask is fabricated by doping a surface region of a semiconductor wafer to render that region resistant to a particular etchant, machining cavities in the surface of the wafer opposite the doped surface to a depth that does not quite reach the doping region, forming pattern openings in the webs remaining across the ends of the cavities, and thinning the webs by exposure to the particular enameling.
Abstract: A shadow mask particularly useful in ion implantation processes is disclosed. The mask is fabricated by doping a surface region of a semiconductor wafer to render that region resistant to a particular etchant, machining cavities in the surface of the wafer opposite the doped surface to a depth that does not quite reach the doped region, forming pattern openings in the webs remaining across the ends of the cavities, and thinning the webs by exposure to the particular etchant until the undoped material in the webs is removed. Thus, the ultimate thickness of the webs is controlled substantially by the doping depth.

Patent
16 Jan 1975
TL;DR: In this paper, a method of aligning a wafer beneath a mask comprising forming a plurality of spaced-apart steps of predetermined length on a semiconductor wafer such that the edges of the steps define a pattern of parallel lines is presented.
Abstract: A method of aligning a wafer beneath a mask comprising forming a plurality of spaced-apart steps of predetermined length on a wafer such that the edges of the steps define a pattern of parallel lines, positioning the wafer beneath a mask having symmetrical openings spaced-apart by a distance substantially equal to the predetermined length such that the ends of the steps appear under the openings, illuminating the wafer with rays of light directed parallel to a plane perpendicular to the edges and incident upon the edges at an oblique angle relative to the top surface of the wafer, simultaneously detecting first diffraction scattered light emanating from one end of the steps and passing through one of the openings and second diffraction scattered light emanating from the other end of the steps and passing through the other of the openings, and moving the wafer relative to the mask until the first light has a predetermined relationship to the second light, and system therefor. In the preferred embodiment the steps form an alternating series of ridges and grooves. By remotely placing a second set of steps perpendicular to the direction of the first set, and a third set of steps parallel to the first set of steps, a complete and accurate alignment of the wafer beneath the mask is achieved. This method lends itself to aligning a unique semiconductor wafer that includes steps formed in a scribe channel separating a pair of adjacent chips.

Patent
29 Dec 1975
TL;DR: In this article, the authors propose a device to facilitate electrical measurement, including step-and-repeat measurement of minute circuits on a semiconductor wafer by placing the wafer in a specific, angular and cartesian coordinate position with respect to a certain orientation of a disc-like pallet of somewhat larger diameter than the Wafer.
Abstract: A device to facilitate electrical measurement, including step-and-repeat measurement of minute circuits on a semiconductor wafer by placing the wafer in a specific, angular and cartesian coordinate position with respect to a certain orientation of a disc-like pallet of somewhat larger diameter than the wafer. The apparatus includes a stack of available pallets, each having an indexing portion, arms to engage the pallet in turn and to interfit with the indexing portion, a translational motion device to move the arms and pallet to another specific location to receive the wafer, a controllable section device to hold the wafer and to rotate it about a vertical axis, and a further controlled guide device to move the arms and wafer in specific X and Y directions to a predetermined orientation. The device includes a connection between each pallet and an evacuating apparatus to affix the wafer to the pallet by suction when the wafer is released from the suction device on the orienting structure. The apparatus further includes a receiving structure to receive pallets with wafers affixed thereto. In addition, the pallets and wafers are subsequently moved from a stack of untested wafers to testing apparatus that includes probes arranged to engage specific minute areas on the wafers. One of the probes includes electrical contact means to be energized by engagement with the surface of the wafer and to control additional movement of the probes toward the surface to a specific amount to exert a predetermined pressure by the probes on the wafer. After testing, the pallets with tested wafers are moved to a location set aside therefore.

Patent
Robert A. Jarvela1
31 Mar 1975
TL;DR: In this paper, a high density low profile air cooled wafer package including flip chip and embedded logic or memory islands was mounted within a heat dissipating cover, with pressure being applied to the interface by partially deflected electrical connectors secured there between.
Abstract: A high density low profile air cooled wafer package including flip chip and embedded logic or memory islands upon a wafer package mounted within a heat dissipating cover having improved thermal dissipation. Heat dissipation is achieved through a thermal grease interface provided between the wafer carrier and the heatsink cover, with pressure being applied to the interface by partially deflected electrical connectors secured there between.

Patent
28 Nov 1975
TL;DR: In this article, the process involves forming porous silicon regions in the surface of the semiconductor body such as a silicon wafer, in the areas where dielectric isolation between semiconductor devices is desired.
Abstract: A semiconductor device, such as a transistor, integrated circuit or the like, having a pattern of oxidized and densified porous silicon regions extending onto one of its major surfaces for isolating regions of the semiconductor is manufacturable by a relatively simple process. The process involves forming porous silicon regions in the surface of the semiconductor body such as a silicon wafer, in the areas where dielectric isolation between semiconductor devices is desired. The porous silicon regions are then oxidized at a temperature sufficient to completely oxidize the porous silicon. The oxidiation is such that the oxidized porous silicon extends above the surface of the semiconductor wafer. The oxidized porous silicon regions are then subjected to a temperature higher than the oxidizing temperature utilized in the previous step to cause the densification of the oxidized porous silicon regions. The result of this densification step is the collapse of the porous oxide to a dense structure which is substantially planar with the surface of the semiconductor wafer. This densified silicon dioxide structure has an etch rate which is substantially the same as thermally grown silicon dioxide.

Patent
04 Jun 1975
TL;DR: In this paper, a semiconductor integrated circuit device of the beam lead type is presented, which is composed of an interconnection substrate with apertures for integrated circuit chips therein and with metallization patterns having sharply pointed ends for penetrating oxide layers over the bonding pads of the chips and for making electrical connection.
Abstract: A semiconductor integrated circuit device of the beam lead type having a semiconductor interconnection substrate with apertures for integrated circuit chips therein and with metallization patterns having sharply pointed ends for penetrating oxide layers over the bonding pads of the chips and for making electrical connection thereto. Devices thus produced may be assembled and tested and failed chips replaced as necessary before the chips are ultrasonically welded to the interconnection metallization and before final fabrication of the device. The invention also includes a method for producing an interconnection substrate in which a plurality of conically shaped holes are etched into a semiconductor wafer having sharp points within the body of the wafer. A metal layer is deposited over the surface of the semiconductor wafer filling the etched holes. Sharp points are thus formed on the metal in the etched holes. Apertures are then etched in the semiconductor wafer and the metal layer etched as required to provide sharply pointed connecting probes suspended above apertures in the semiconductor wafer.

Patent
13 Mar 1975
TL;DR: In this paper, a bias voltage is applied between the wafer and the pedestal and anode structure to minimize distortion of the electric field, and also serves to secure and flatten the Wafer against a pedestal by electrostatic attraction.
Abstract: Apparatus and a corresponding method for supporting a wafer of target material for exposure to a beam or pattern of electrons with little or no distortion of the electric field used to accelerate the electrons from a cathode to the target. In one embodiment, the target wafer is supported on a flat pedestal some distance above a surrounding anode structure, and is insulated from the pedestal by a thin dielectric sheet. A bias voltage applied between the wafer and the pedestal and anode structure is selected to minimize distortion of the electric field, and also serves to secure and flatten the wafer against the pedestal by electrostatic attraction. Alternatively, the wafer may be held in position by a retaining lip projecting over the edges of the wafer, the lip having a conductive surface layer insulated by a dielectric layer from the remainder of the lip and from the wafer. Distortion of the electron-accelerating field is minimized by applying an appropriate bias voltage between the wafer and the conductive layer on the lip.

Patent
18 Apr 1975
TL;DR: In this paper, a chlorinated naphthalene and a paraterphenyl are mixed to provide an adhesive for adhering a semiconductor wafer to a support for processing.
Abstract: A chlorinated naphthalene and a paraterphenyl are mixed to provide an adhesive for adhering a semiconductor wafer to a support for processing. The adhesive so formed may be evaporated at the end of processing the wafer, without leaving a residue, to release the devices which have been formed from the wafer.

Patent
15 Oct 1975
TL;DR: In this article, an improved wafer electrode for use in an electrolytic cell, having an access tube to direct a fluid across the electrode plate or to remove fluid from near the electrodes plate within the cell, was described.
Abstract: Disclosed is an improved wafer electrode for use in an electrolytic cell, having an access tube to direct a fluid across the electrode plate or to remove fluid from near the electrode plate within the cell Cells employing the subject wafer electrode in an electrolytic cell can be used for various electrochemical processes such as for the production of alkali metal carbonates

Patent
31 Dec 1975
TL;DR: In this article, metal wires of widths as small as 10 microns are migrated by thermal gradient zone melting processing as a molten zone through a body of semiconductor material, and improved uniform doped regions are produced.
Abstract: Metal wires of widths as small as 10 microns are migrated by thermal gradient zone melting processing as a molten zone through a body of semiconductor material. By calculating the width and thickness of the metal wires deposited on the wafer surface, improved uniform doped regions are produced. The method is restricted to the (100) planar orientation.

Patent
22 Apr 1975
TL;DR: A silicon-gate insulated gate field effect transistor (SGFET) as mentioned in this paper is a transistor with a thin field oxide in contiguous surrounding relation to its gate electrode and with a surface coplanar with or slightly higher than the surface of the gate electrode.
Abstract: A silicon-gate insulated gate field effect transistor device has a thick field oxide in contiguous surrounding relation to its gate electrode and with a surface coplanar with or slightly higher than the surface of the gate electrode, thus facilitating crossovers and contacts to the gate electrode. The method of making this device includes forming a self-aligned silicon gate structure on a silicon wafer, masking the gate structure against the diffusion of oxygen, and thereafter oxidizing the silicon wafer to grow a thick silicon dioxide layer in surrounding relation to the silicon gate structure.

Patent
Else Kooi1
14 Feb 1975
TL;DR: In this paper, a method of making a semiconductor device is described in which a selected surface portion of a silicon wafer is masked against oxidation, and then the surface is oxidized to grow a thermal oxide which sinks into the silicon surface at the unmasked areas, with the result that the masked silicon remains as a mesa surrounded by the sunken oxide.
Abstract: A method of making a semiconductor device is described in which a selected surface portion of a silicon wafer is masked against oxidation, and then the surface is oxidized to grow a thermal oxide which sinks into the silicon surface at the unmasked areas, with the result that the masked silicon remains as a mesa surrounded by the sunken oxide. Then semiconductor devices can be provided by various techniques in the silicon mesa. The advantages include the provision of flat junctions, as distinguished from dish junctions in the prior art, reduced capacitance resulting from the extension of the device interconnections over the silicon wafer, and a flatter surface on top of the wafer reducing the risk of damage to the deposited interconnections.

Patent
07 Nov 1975
TL;DR: In this article, a monometallic batch process for forming beam leads of a preferred metal such as aluminum or gold is applied to a wafer of finished microelectronic devices already having metal contact pads of the same preferred metal.
Abstract: A monometallic batch process for forming beam leads of a preferred metal such as aluminum or gold. The process is applied to a wafer of finished microelectronic devices already having metal contact pads of the same preferred metal. Where aluminum is the desired metal, high deposition rates are used to minimize aluminum oxide contamination. High yield is achieved by forming the beam leads to have an elevated cantilevered configuration, by deep scribing of the wafer and, when desired, by providing an energy absorbing cushion to reduce the effect of collisions between chip edges and beam leads.

Patent
01 Dec 1975
TL;DR: In this article, a light-emitting diode element comprises a semiconductor wafer including a pair of a p-type semiconductor region and an n-type region forming a pn junction.
Abstract: A light-emitting diode element comprises a semiconductor wafer including a pair of a p-type semiconductor region and an n-type semiconductor region forming a pn junction, an inclined first electrode provided on at least one of the peripheral edges of the surface of one of the semiconductor regions in the semiconductor wafer, and a flat second electrode provided on the surface of the other semiconductor region. A light-emitting diode device is provided in which a plurality of such light-emitting diode elements are respectively received in a plurality of openings of a substrate having a first wiring conductor group and a second wiring conductor group electrically connected to the first and second electrodes respectively of the light-emitting diode elements by a low-melting metal. Thus, these light-emitting diode elements can be mounted on the single substrate in a high package density, and the light-emitting diode device of simple construction can be easily assembled.